Skip to content

Commit db3792b

Browse files
topperctopperc
authored
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (llvm#107011)
All of the test changes are because integer type legalization prefers to promote fp_to_uint to fp_to_sint if neither is "Legal".
1 parent 18cf14e commit db3792b

File tree

8 files changed

+82
-90
lines changed

8 files changed

+82
-90
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 31 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
460460
setOperationAction(ISD::FABS, MVT::bf16, Custom);
461461
setOperationAction(ISD::FNEG, MVT::bf16, Custom);
462462
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Custom);
463+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
463464
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
464465
}
465466

@@ -479,6 +480,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
479480
setOperationAction(ISD::FABS, MVT::f16, Custom);
480481
setOperationAction(ISD::FNEG, MVT::f16, Custom);
481482
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
483+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
482484
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, XLenVT, Custom);
483485
}
484486

@@ -592,8 +594,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
592594
setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
593595
Custom);
594596

597+
// f16/bf16 require custom handling.
595598
setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT}, XLenVT,
596-
Legal);
599+
Custom);
597600
setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP}, XLenVT,
598601
Custom);
599602

@@ -3096,6 +3099,31 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
30963099
return Res;
30973100
}
30983101

3102+
static SDValue lowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3103+
const RISCVSubtarget &Subtarget) {
3104+
bool IsStrict = Op->isStrictFPOpcode();
3105+
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
3106+
3107+
// f16 conversions are promoted to f32 when Zfh/Zhinx is not enabled.
3108+
// bf16 conversions are always promoted to f32.
3109+
if ((SrcVal.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) ||
3110+
SrcVal.getValueType() == MVT::bf16) {
3111+
SDLoc DL(Op);
3112+
if (IsStrict) {
3113+
SDValue Ext =
3114+
DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
3115+
{Op.getOperand(0), SrcVal});
3116+
return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
3117+
{Ext.getValue(1), Ext.getValue(0)});
3118+
}
3119+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
3120+
DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, SrcVal));
3121+
}
3122+
3123+
// Other operations are legal.
3124+
return Op;
3125+
}
3126+
30993127
static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
31003128
switch (Opc) {
31013129
case ISD::FROUNDEVEN:
@@ -6661,6 +6689,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
66616689
// the source. We custom-lower any conversions that do two hops into
66626690
// sequences.
66636691
MVT VT = Op.getSimpleValueType();
6692+
if (VT.isScalarInteger())
6693+
return lowerFP_TO_INT(Op, DAG, Subtarget);
66646694
bool IsStrict = Op->isStrictFPOpcode();
66656695
SDValue Src = Op.getOperand(0 + IsStrict);
66666696
MVT SrcVT = Src.getSimpleValueType();

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -58,20 +58,6 @@ def : Pat<(riscv_fmv_x_anyexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
5858
def : Pat<(riscv_fmv_x_signexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
5959
} // Predicates = [HasStdExtZfbfmin]
6060

61-
let Predicates = [HasStdExtZfbfmin] in {
62-
// bf16->[u]int. Round-to-zero must be used for the f32->int step, the
63-
// rounding mode has no effect for bf16->f32.
64-
def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
65-
def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
66-
}
67-
68-
let Predicates = [HasStdExtZfbfmin, IsRV64] in {
69-
// bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
70-
// rounding mode has no effect for bf16->f32.
71-
def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
72-
def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
73-
}
74-
7561
let Predicates = [HasStdExtZfbfmin, HasStdExtD] in {
7662
// bf16 -> f64
7763
def : Pat<(fpextend (bf16 FPR16:$rs1)),

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -599,27 +599,3 @@ def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2),
599599
(FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>;
600600
def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H_INX $rs2, FRM_RNE))>;
601601
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]
602-
603-
let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
604-
// half->[u]int. Round-to-zero must be used.
605-
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
606-
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
607-
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]
608-
609-
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
610-
// half->[u]int. Round-to-zero must be used.
611-
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
612-
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
613-
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx]
614-
615-
let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
616-
// half->[u]int64. Round-to-zero must be used.
617-
def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
618-
def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
619-
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
620-
621-
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
622-
// half->[u]int64. Round-to-zero must be used.
623-
def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
624-
def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
625-
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64]

‎llvm/test/CodeGen/RISCV/bfloat-convert.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
121121
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
122122
; CHECK32ZFBFMIN: # %bb.0:
123123
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
124-
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
124+
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
125125
; CHECK32ZFBFMIN-NEXT: ret
126126
;
127127
; RV32ID-LABEL: fcvt_ui_bf16:
@@ -135,7 +135,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
135135
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
136136
; CHECK64ZFBFMIN: # %bb.0:
137137
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
138-
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
138+
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
139139
; CHECK64ZFBFMIN-NEXT: ret
140140
;
141141
; RV64ID-LABEL: fcvt_ui_bf16:
@@ -1568,7 +1568,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
15681568
; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
15691569
; CHECK32ZFBFMIN: # %bb.0:
15701570
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1571-
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1571+
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
15721572
; CHECK32ZFBFMIN-NEXT: ret
15731573
;
15741574
; RV32ID-LABEL: fcvt_wu_s_i8:

‎llvm/test/CodeGen/RISCV/half-convert-strict.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -136,78 +136,78 @@ declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
136136
define i16 @fcvt_ui_h(half %a) nounwind strictfp {
137137
; RV32IZFH-LABEL: fcvt_ui_h:
138138
; RV32IZFH: # %bb.0:
139-
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
139+
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
140140
; RV32IZFH-NEXT: ret
141141
;
142142
; RV64IZFH-LABEL: fcvt_ui_h:
143143
; RV64IZFH: # %bb.0:
144-
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
144+
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
145145
; RV64IZFH-NEXT: ret
146146
;
147147
; RV32IZHINX-LABEL: fcvt_ui_h:
148148
; RV32IZHINX: # %bb.0:
149-
; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
149+
; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
150150
; RV32IZHINX-NEXT: ret
151151
;
152152
; RV64IZHINX-LABEL: fcvt_ui_h:
153153
; RV64IZHINX: # %bb.0:
154-
; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
154+
; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
155155
; RV64IZHINX-NEXT: ret
156156
;
157157
; RV32IDZFH-LABEL: fcvt_ui_h:
158158
; RV32IDZFH: # %bb.0:
159-
; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
159+
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
160160
; RV32IDZFH-NEXT: ret
161161
;
162162
; RV64IDZFH-LABEL: fcvt_ui_h:
163163
; RV64IDZFH: # %bb.0:
164-
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
164+
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
165165
; RV64IDZFH-NEXT: ret
166166
;
167167
; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
168168
; RV32IZDINXZHINX: # %bb.0:
169-
; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
169+
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
170170
; RV32IZDINXZHINX-NEXT: ret
171171
;
172172
; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
173173
; RV64IZDINXZHINX: # %bb.0:
174-
; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
174+
; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
175175
; RV64IZDINXZHINX-NEXT: ret
176176
;
177177
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
178178
; CHECK32-IZFHMIN: # %bb.0:
179179
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
180-
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
180+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
181181
; CHECK32-IZFHMIN-NEXT: ret
182182
;
183183
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
184184
; CHECK64-IZFHMIN: # %bb.0:
185185
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
186-
; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
186+
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
187187
; CHECK64-IZFHMIN-NEXT: ret
188188
;
189189
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
190190
; CHECK32-IZHINXMIN: # %bb.0:
191191
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
192-
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
192+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
193193
; CHECK32-IZHINXMIN-NEXT: ret
194194
;
195195
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
196196
; CHECK64-IZHINXMIN: # %bb.0:
197197
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
198-
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
198+
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
199199
; CHECK64-IZHINXMIN-NEXT: ret
200200
;
201201
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
202202
; CHECK32-IZDINXZHINXMIN: # %bb.0:
203203
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
204-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
204+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
205205
; CHECK32-IZDINXZHINXMIN-NEXT: ret
206206
;
207207
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
208208
; CHECK64-IZDINXZHINXMIN: # %bb.0:
209209
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
210-
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
210+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
211211
; CHECK64-IZDINXZHINXMIN-NEXT: ret
212212
%1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict")
213213
ret i16 %1

‎llvm/test/CodeGen/RISCV/half-convert.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -672,37 +672,37 @@ define i16 @fcvt_ui_h(half %a) nounwind {
672672
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
673673
; CHECK32-IZFHMIN: # %bb.0:
674674
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
675-
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
675+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
676676
; CHECK32-IZFHMIN-NEXT: ret
677677
;
678678
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
679679
; CHECK64-IZFHMIN: # %bb.0:
680680
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
681-
; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
681+
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
682682
; CHECK64-IZFHMIN-NEXT: ret
683683
;
684684
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
685685
; CHECK32-IZHINXMIN: # %bb.0:
686686
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
687-
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
687+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
688688
; CHECK32-IZHINXMIN-NEXT: ret
689689
;
690690
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
691691
; CHECK64-IZHINXMIN: # %bb.0:
692692
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
693-
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
693+
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
694694
; CHECK64-IZHINXMIN-NEXT: ret
695695
;
696696
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
697697
; CHECK32-IZDINXZHINXMIN: # %bb.0:
698698
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
699-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
699+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
700700
; CHECK32-IZDINXZHINXMIN-NEXT: ret
701701
;
702702
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
703703
; CHECK64-IZDINXZHINXMIN: # %bb.0:
704704
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
705-
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
705+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
706706
; CHECK64-IZDINXZHINXMIN-NEXT: ret
707707
%1 = fptoui half %a to i16
708708
ret i16 %1
@@ -6793,7 +6793,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
67936793
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i16:
67946794
; CHECK32-IZFHMIN: # %bb.0:
67956795
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
6796-
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
6796+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
67976797
; CHECK32-IZFHMIN-NEXT: ret
67986798
;
67996799
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i16:
@@ -6805,7 +6805,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
68056805
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i16:
68066806
; CHECK32-IZHINXMIN: # %bb.0:
68076807
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
6808-
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
6808+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
68096809
; CHECK32-IZHINXMIN-NEXT: ret
68106810
;
68116811
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i16:
@@ -6817,7 +6817,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
68176817
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
68186818
; CHECK32-IZDINXZHINXMIN: # %bb.0:
68196819
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
6820-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
6820+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
68216821
; CHECK32-IZDINXZHINXMIN-NEXT: ret
68226822
;
68236823
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
@@ -7744,7 +7744,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
77447744
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i8:
77457745
; CHECK32-IZFHMIN: # %bb.0:
77467746
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
7747-
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
7747+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
77487748
; CHECK32-IZFHMIN-NEXT: ret
77497749
;
77507750
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i8:
@@ -7756,7 +7756,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
77567756
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i8:
77577757
; CHECK32-IZHINXMIN: # %bb.0:
77587758
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
7759-
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
7759+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
77607760
; CHECK32-IZHINXMIN-NEXT: ret
77617761
;
77627762
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i8:
@@ -7768,7 +7768,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
77687768
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
77697769
; CHECK32-IZDINXZHINXMIN: # %bb.0:
77707770
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
7771-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
7771+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
77727772
; CHECK32-IZDINXZHINXMIN-NEXT: ret
77737773
;
77747774
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:

0 commit comments

Comments
 (0)