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AMDGPU/Uniformity/GlobalISel: G_AMDGPU atomics are always divergent
Patch by: Acim Maravic Differential Revision: https://reviews.llvm.org/D157091
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-1
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4 files changed

+100
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8662,7 +8662,8 @@ SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
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if (SIInstrInfo::isGenericAtomicRMWOpcode(opcode) ||
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opcode == AMDGPU::G_ATOMIC_CMPXCHG ||
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opcode == AMDGPU::G_ATOMIC_CMPXCHG_WITH_SUCCESS) {
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opcode == AMDGPU::G_ATOMIC_CMPXCHG_WITH_SUCCESS ||
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AMDGPU::isGenericAtomic(opcode)) {
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return InstructionUniformity::NeverUniform;
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}
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return InstructionUniformity::Default;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,28 @@ bool isPermlane16(unsigned Opc) {
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Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11;
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}
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bool isGenericAtomic(unsigned Opc) {
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return Opc == AMDGPU::G_AMDGPU_ATOMIC_FMIN ||
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Opc == AMDGPU::G_AMDGPU_ATOMIC_FMAX ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
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Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
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Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
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}
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515537
bool isTrue16Inst(unsigned Opc) {
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const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
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return Info ? Info->IsTrue16 : false;

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -547,6 +547,9 @@ bool isMAC(unsigned Opc);
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LLVM_READNONE
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bool isPermlane16(unsigned Opc);
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LLVM_READNONE
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bool isGenericAtomic(unsigned Opc);
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namespace VOPD {
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enum Component : unsigned {

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,3 +85,76 @@ body: |
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SI_RETURN implicit $vgpr0
8686
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...
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---
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name: test_buffer_atomics_always_divergent
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $sgpr0, $sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
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%0:_(s32) = COPY $sgpr0
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%1:sgpr(p0) = COPY $sgpr2_sgpr3
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%2:_(s32) = IMPLICIT_DEF
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%3:_(<4 x s32>) = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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%4:_(s32) = G_CONSTANT i32 0
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_ATOMIC_FMIN
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%5:_(s32) = G_AMDGPU_ATOMIC_FMIN %0, %3
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_ATOMIC_FMAX
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%6:_(s32) = G_AMDGPU_ATOMIC_FMAX %0, %3
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SWAP
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%7:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SWAP %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_ADD
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%8:_(s32) = G_AMDGPU_BUFFER_ATOMIC_ADD %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SUB
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%9:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SUB %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SMIN
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%10:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SMIN %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_UMIN
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%11:_(s32) = G_AMDGPU_BUFFER_ATOMIC_UMIN %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SMAX
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%12:_(s32) = G_AMDGPU_BUFFER_ATOMIC_SMAX %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_UMAX
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%13:_(s32) = G_AMDGPU_BUFFER_ATOMIC_UMAX %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_AND
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%14:_(s32) = G_AMDGPU_BUFFER_ATOMIC_AND %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_OR
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%15:_(s32) = G_AMDGPU_BUFFER_ATOMIC_OR %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_XOR
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%16:_(s32) = G_AMDGPU_BUFFER_ATOMIC_XOR %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_INC
139+
%17:_(s32) = G_AMDGPU_BUFFER_ATOMIC_INC %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_DEC
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%18:_(s32) = G_AMDGPU_BUFFER_ATOMIC_DEC %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD
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%19:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FMIN
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%20:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FMIN %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FMAX
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%21:_(s32) = G_AMDGPU_BUFFER_ATOMIC_FMAX %0, %3, %4, %4, %4, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_AMDGPU_BUFFER_ATOMIC_CMPSWAP
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%22:_(s32) = G_AMDGPU_BUFFER_ATOMIC_CMPSWAP %0, %4, %3, %2, %2, %2, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 8)
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; CHECK: DIVERGENT
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; CHECK-SAME: G_AMDGPU_ATOMIC_CMPXCHG
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%23:vgpr(s32) = G_AMDGPU_ATOMIC_CMPXCHG %1, %4 :: (load store seq_cst (s32), addrspace 0)
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...

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