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[NFC][AMDGPU][CostModel] Add tests for AMDGPU cost model.
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‎llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -575,5 +575,107 @@ define amdgpu_kernel void @rcp_ftzdaz() #1 {
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ret void
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}
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define i32 @frem(i32 %arg) {
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; CIFASTF64-LABEL: 'frem'
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %F32 = frem float undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V4F32 = frem <4 x float> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V8F32 = frem <8 x float> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %V16F32 = frem <16 x float> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %F64 = frem double undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2F64 = frem <2 x double> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4F64 = frem <4 x double> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 576 for instruction: %V8F64 = frem <8 x double> undef, undef
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; CIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; CISLOWF64-LABEL: 'frem'
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %F32 = frem float undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V4F32 = frem <4 x float> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V8F32 = frem <8 x float> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %V16F32 = frem <16 x float> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %F64 = frem double undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V2F64 = frem <2 x double> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 152 for instruction: %V4F64 = frem <4 x double> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 912 for instruction: %V8F64 = frem <8 x double> undef, undef
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; CISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; SIFASTF64-LABEL: 'frem'
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %F32 = frem float undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V4F32 = frem <4 x float> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V8F32 = frem <8 x float> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %V16F32 = frem <16 x float> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %F64 = frem double undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %V2F64 = frem <2 x double> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %V4F64 = frem <4 x double> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 648 for instruction: %V8F64 = frem <8 x double> undef, undef
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; SIFASTF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; SISLOWF64-LABEL: 'frem'
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %F32 = frem float undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V4F32 = frem <4 x float> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V8F32 = frem <8 x float> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %V16F32 = frem <16 x float> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %F64 = frem double undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V2F64 = frem <2 x double> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 164 for instruction: %V4F64 = frem <4 x double> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 984 for instruction: %V8F64 = frem <8 x double> undef, undef
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; SISLOWF64-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; FP16-LABEL: 'frem'
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; FP16-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %F32 = frem float undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %V4F32 = frem <4 x float> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %V8F32 = frem <8 x float> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %V16F32 = frem <16 x float> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %F64 = frem double undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V2F64 = frem <2 x double> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 152 for instruction: %V4F64 = frem <4 x double> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 912 for instruction: %V8F64 = frem <8 x double> undef, undef
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; FP16-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; CI-SIZE-LABEL: 'frem'
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %F32 = frem float undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V4F32 = frem <4 x float> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F32 = frem <8 x float> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 576 for instruction: %V16F32 = frem <16 x float> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %F64 = frem double undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V2F64 = frem <2 x double> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V4F64 = frem <4 x double> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %V8F64 = frem <8 x double> undef, undef
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; CI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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;
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; SI-SIZE-LABEL: 'frem'
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %F32 = frem float undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V4F32 = frem <4 x float> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F32 = frem <8 x float> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 576 for instruction: %V16F32 = frem <16 x float> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %F64 = frem double undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %V2F64 = frem <2 x double> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 100 for instruction: %V4F64 = frem <4 x double> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 600 for instruction: %V8F64 = frem <8 x double> undef, undef
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; SI-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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;
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; FP16-SIZE-LABEL: 'frem'
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %F32 = frem float undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V4F32 = frem <4 x float> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F32 = frem <8 x float> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 576 for instruction: %V16F32 = frem <16 x float> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %F64 = frem double undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V2F64 = frem <2 x double> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %V4F64 = frem <4 x double> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %V8F64 = frem <8 x double> undef, undef
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; FP16-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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;
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%F32 = frem float undef, undef
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%V4F32 = frem <4 x float> undef, undef
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%V8F32 = frem <8 x float> undef, undef
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%V16F32 = frem <16 x float> undef, undef
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%F64 = frem double undef, undef
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%V2F64 = frem <2 x double> undef, undef
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%V4F64 = frem <4 x double> undef, undef
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%V8F64 = frem <8 x double> undef, undef
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ret i32 undef
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}
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attributes #0 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
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attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }

‎llvm/test/Analysis/CostModel/AMDGPU/fneg.ll

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,3 +89,39 @@ define amdgpu_kernel void @fneg_f16() {
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%v17f16 = fneg <17 x half> undef
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ret void
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}
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define i32 @fneg_idiom(i32 %arg) {
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; CHECK-LABEL: 'fneg_idiom'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
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;
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; SIZE-LABEL: 'fneg_idiom'
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = fsub double -0.000000e+00, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8F64 = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, undef
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; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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;
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%F32 = fsub float -0.0, undef
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%V4F32 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
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%V8F32 = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
119+
%V16F32 = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
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%F64 = fsub double -0.0, undef
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%V2F64 = fsub <2 x double> <double -0.0, double -0.0>, undef
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%V4F64 = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, undef
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%V8F64 = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, undef
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ret i32 undef
127+
}

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