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[X86] Fix some clang-tidy bugprone-argument-comment issues
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3 files changed

+33
-30
lines changed

3 files changed

+33
-30
lines changed

‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2146,7 +2146,7 @@ unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
21462146
SMLoc Start = Tok.getLoc(), End;
21472147
StringRef Identifier = Tok.getString();
21482148
if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2149-
/*Unevaluated=*/true, End))
2149+
/*IsUnevaluatedOperand=*/true, End))
21502150
return 0;
21512151

21522152
if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {

‎llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 29 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1231,13 +1231,15 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
12311231
if (SrcVT == MVT::i1) {
12321232
if (Outs[0].Flags.isSExt())
12331233
return false;
1234-
SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
1234+
// TODO
1235+
SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*Op0IsKill=*/false);
12351236
SrcVT = MVT::i8;
12361237
}
12371238
unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
12381239
ISD::SIGN_EXTEND;
1239-
SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1240-
SrcReg, /*TODO: Kill=*/false);
1240+
// TODO
1241+
SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg,
1242+
/*Op0IsKill=*/false);
12411243
}
12421244

12431245
// Make the copy.
@@ -1431,8 +1433,8 @@ bool X86FastISel::X86SelectCmp(const Instruction *I) {
14311433
ResultReg = createResultReg(&X86::GR32RegClass);
14321434
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
14331435
ResultReg);
1434-
ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, /*Kill=*/true,
1435-
X86::sub_8bit);
1436+
ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg,
1437+
/*Op0IsKill=*/true, X86::sub_8bit);
14361438
if (!ResultReg)
14371439
return false;
14381440
break;
@@ -1555,11 +1557,11 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) {
15551557
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8),
15561558
Result32).addReg(ResultReg);
15571559

1558-
ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
1559-
X86::sub_16bit);
1560+
ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32,
1561+
/*Op0IsKill=*/true, X86::sub_16bit);
15601562
} else if (DstVT != MVT::i8) {
15611563
ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1562-
ResultReg, /*Kill=*/true);
1564+
ResultReg, /*Op0IsKill=*/true);
15631565
if (ResultReg == 0)
15641566
return false;
15651567
}
@@ -1601,11 +1603,11 @@ bool X86FastISel::X86SelectSExt(const Instruction *I) {
16011603
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8),
16021604
Result32).addReg(ResultReg);
16031605

1604-
ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
1605-
X86::sub_16bit);
1606+
ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32,
1607+
/*Op0IsKill=*/true, X86::sub_16bit);
16061608
} else if (DstVT != MVT::i8) {
16071609
ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND,
1608-
ResultReg, /*Kill=*/true);
1610+
ResultReg, /*Op0IsKill=*/true);
16091611
if (ResultReg == 0)
16101612
return false;
16111613
}
@@ -1757,7 +1759,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
17571759
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
17581760
TII.get(TargetOpcode::COPY), OpReg)
17591761
.addReg(KOpReg);
1760-
OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true,
1762+
OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Op0IsKill=*/true,
17611763
X86::sub_8bit);
17621764
}
17631765
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
@@ -1989,7 +1991,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
19891991

19901992
// Now reference the 8-bit subreg of the result.
19911993
ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg,
1992-
/*Kill=*/true, X86::sub_8bit);
1994+
/*Op0IsKill=*/true, X86::sub_8bit);
19931995
}
19941996
// Copy the result out of the physreg if we haven't already.
19951997
if (!ResultReg) {
@@ -2103,7 +2105,7 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
21032105
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
21042106
TII.get(TargetOpcode::COPY), CondReg)
21052107
.addReg(KCondReg, getKillRegState(CondIsKill));
2106-
CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
2108+
CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Op0IsKill=*/true,
21072109
X86::sub_8bit);
21082110
}
21092111
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
@@ -2257,12 +2259,12 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
22572259
const TargetRegisterClass *VR128 = &X86::VR128RegClass;
22582260
Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill,
22592261
CmpRHSReg, CmpRHSIsKill, CC);
2260-
Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, /*IsKill=*/false,
2261-
LHSReg, LHSIsKill);
2262-
Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, /*IsKill=*/true,
2263-
RHSReg, RHSIsKill);
2264-
Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*IsKill=*/true,
2265-
AndReg, /*IsKill=*/true);
2262+
Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg,
2263+
/*Op0IsKill=*/false, LHSReg, LHSIsKill);
2264+
Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg,
2265+
/*Op0IsKill=*/true, RHSReg, RHSIsKill);
2266+
Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, /*Op0IsKill=*/true,
2267+
AndReg, /*Op1IsKill=*/true);
22662268
ResultReg = createResultReg(RC);
22672269
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
22682270
TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg);
@@ -2321,7 +2323,7 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
23212323
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
23222324
TII.get(TargetOpcode::COPY), CondReg)
23232325
.addReg(KCondReg, getKillRegState(CondIsKill));
2324-
CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Kill=*/true,
2326+
CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, /*Op0IsKill=*/true,
23252327
X86::sub_8bit);
23262328
}
23272329
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
@@ -2578,7 +2580,7 @@ bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
25782580

25792581
unsigned Reg;
25802582
bool RV = X86FastEmitLoad(VT, SrcAM, nullptr, Reg);
2581-
RV &= X86FastEmitStore(VT, Reg, /*Kill=*/true, DestAM);
2583+
RV &= X86FastEmitStore(VT, Reg, /*ValIsKill=*/true, DestAM);
25822584
assert(RV && "Failed to emit load or store??");
25832585

25842586
unsigned Size = VT.getSizeInBits()/8;
@@ -2642,15 +2644,15 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
26422644
assert(Op->getType()->isIntegerTy(16) && "Expected a 16-bit integer!");
26432645
// Explicitly zero-extend the input to 32-bit.
26442646
InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg,
2645-
/*Kill=*/false);
2647+
/*Op0IsKill=*/false);
26462648

26472649
// The following SCALAR_TO_VECTOR will be expanded into a VMOVDI2PDIrr.
26482650
InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR,
2649-
InputReg, /*Kill=*/true);
2651+
InputReg, /*Op0IsKill=*/true);
26502652

26512653
unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr
26522654
: X86::VCVTPH2PSrr;
2653-
InputReg = fastEmitInst_r(Opc, RC, InputReg, /*Kill=*/true);
2655+
InputReg = fastEmitInst_r(Opc, RC, InputReg, /*Op0IsKill=*/true);
26542656

26552657
// The result value is in the lower 32-bits of ResultReg.
26562658
// Emit an explicit copy from register class VR128 to register class FR32.
@@ -3692,10 +3694,10 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
36923694
default: llvm_unreachable("Unexpected value type");
36933695
case MVT::i1:
36943696
case MVT::i8:
3695-
return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
3697+
return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Op0IsKill=*/true,
36963698
X86::sub_8bit);
36973699
case MVT::i16:
3698-
return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
3700+
return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Op0IsKill=*/true,
36993701
X86::sub_16bit);
37003702
case MVT::i32:
37013703
return SrcReg;

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3754,7 +3754,7 @@ SDValue X86TargetLowering::LowerFormalArguments(
37543754
// same, so the size of funclets' (mostly empty) frames is dictated by
37553755
// how far this slot is from the bottom (since they allocate just enough
37563756
// space to accommodate holding this slot at the correct offset).
3757-
int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSS=*/false);
3757+
int PSPSymFI = MFI.CreateStackObject(8, Align(8), /*isSpillSlot=*/false);
37583758
EHInfo->PSPSymFrameIdx = PSPSymFI;
37593759
}
37603760
}
@@ -24315,7 +24315,8 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2431524315
SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
2431624316
SDValue VAARG = DAG.getMemIntrinsicNode(
2431724317
X86ISD::VAARG_64, dl, VTs, InstOps, MVT::i64, MachinePointerInfo(SV),
24318-
/*Align=*/None, MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
24318+
/*Alignment=*/None,
24319+
MachineMemOperand::MOLoad | MachineMemOperand::MOStore);
2431924320
Chain = VAARG.getValue(1);
2432024321

2432124322
// Load the next argument and return it

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