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[RISCV] Move vector pseudo hasAllNBitUsers switch into RISCVInstrInfo. NFC (llvm#67593)
The handling for vector pseudos in hasAllNBitUsers is duplicated across RISCVISelDAGToDAG and RISCVOptWInstrs. This deduplicates it between the two, with the common denominator between the two call sites being the opcode and SEW: We need to handle extracting these separately since one operates at the SelectionDAG level and the other at the MachineInstr level.
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4 files changed

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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 3 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -2779,120 +2779,9 @@ static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
27792779
if (UserOpNo == VLIdx)
27802780
return false;
27812781

2782-
// TODO: Handle Zvbb instructions
2783-
switch (PseudoInfo->BaseInstr) {
2784-
default:
2785-
return false;
2786-
2787-
// 11.6. Vector Single-Width Shift Instructions
2788-
case RISCV::VSLL_VX:
2789-
case RISCV::VSRL_VX:
2790-
case RISCV::VSRA_VX:
2791-
// 12.4. Vector Single-Width Scaling Shift Instructions
2792-
case RISCV::VSSRL_VX:
2793-
case RISCV::VSSRA_VX:
2794-
// Only the low lg2(SEW) bits of the shift-amount value are used.
2795-
if (Bits < Log2SEW)
2796-
return false;
2797-
break;
2798-
2799-
// 11.7 Vector Narrowing Integer Right Shift Instructions
2800-
case RISCV::VNSRL_WX:
2801-
case RISCV::VNSRA_WX:
2802-
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
2803-
case RISCV::VNCLIPU_WX:
2804-
case RISCV::VNCLIP_WX:
2805-
// Only the low lg2(2*SEW) bits of the shift-amount value are used.
2806-
if (Bits < Log2SEW + 1)
2807-
return false;
2808-
break;
2809-
2810-
// 11.1. Vector Single-Width Integer Add and Subtract
2811-
case RISCV::VADD_VX:
2812-
case RISCV::VSUB_VX:
2813-
case RISCV::VRSUB_VX:
2814-
// 11.2. Vector Widening Integer Add/Subtract
2815-
case RISCV::VWADDU_VX:
2816-
case RISCV::VWSUBU_VX:
2817-
case RISCV::VWADD_VX:
2818-
case RISCV::VWSUB_VX:
2819-
case RISCV::VWADDU_WX:
2820-
case RISCV::VWSUBU_WX:
2821-
case RISCV::VWADD_WX:
2822-
case RISCV::VWSUB_WX:
2823-
// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2824-
case RISCV::VADC_VXM:
2825-
case RISCV::VADC_VIM:
2826-
case RISCV::VMADC_VXM:
2827-
case RISCV::VMADC_VIM:
2828-
case RISCV::VMADC_VX:
2829-
case RISCV::VSBC_VXM:
2830-
case RISCV::VMSBC_VXM:
2831-
case RISCV::VMSBC_VX:
2832-
// 11.5 Vector Bitwise Logical Instructions
2833-
case RISCV::VAND_VX:
2834-
case RISCV::VOR_VX:
2835-
case RISCV::VXOR_VX:
2836-
// 11.8. Vector Integer Compare Instructions
2837-
case RISCV::VMSEQ_VX:
2838-
case RISCV::VMSNE_VX:
2839-
case RISCV::VMSLTU_VX:
2840-
case RISCV::VMSLT_VX:
2841-
case RISCV::VMSLEU_VX:
2842-
case RISCV::VMSLE_VX:
2843-
case RISCV::VMSGTU_VX:
2844-
case RISCV::VMSGT_VX:
2845-
// 11.9. Vector Integer Min/Max Instructions
2846-
case RISCV::VMINU_VX:
2847-
case RISCV::VMIN_VX:
2848-
case RISCV::VMAXU_VX:
2849-
case RISCV::VMAX_VX:
2850-
// 11.10. Vector Single-Width Integer Multiply Instructions
2851-
case RISCV::VMUL_VX:
2852-
case RISCV::VMULH_VX:
2853-
case RISCV::VMULHU_VX:
2854-
case RISCV::VMULHSU_VX:
2855-
// 11.11. Vector Integer Divide Instructions
2856-
case RISCV::VDIVU_VX:
2857-
case RISCV::VDIV_VX:
2858-
case RISCV::VREMU_VX:
2859-
case RISCV::VREM_VX:
2860-
// 11.12. Vector Widening Integer Multiply Instructions
2861-
case RISCV::VWMUL_VX:
2862-
case RISCV::VWMULU_VX:
2863-
case RISCV::VWMULSU_VX:
2864-
// 11.13. Vector Single-Width Integer Multiply-Add Instructions
2865-
case RISCV::VMACC_VX:
2866-
case RISCV::VNMSAC_VX:
2867-
case RISCV::VMADD_VX:
2868-
case RISCV::VNMSUB_VX:
2869-
// 11.14. Vector Widening Integer Multiply-Add Instructions
2870-
case RISCV::VWMACCU_VX:
2871-
case RISCV::VWMACC_VX:
2872-
case RISCV::VWMACCSU_VX:
2873-
case RISCV::VWMACCUS_VX:
2874-
// 11.15. Vector Integer Merge Instructions
2875-
case RISCV::VMERGE_VXM:
2876-
// 11.16. Vector Integer Move Instructions
2877-
case RISCV::VMV_V_X:
2878-
// 12.1. Vector Single-Width Saturating Add and Subtract
2879-
case RISCV::VSADDU_VX:
2880-
case RISCV::VSADD_VX:
2881-
case RISCV::VSSUBU_VX:
2882-
case RISCV::VSSUB_VX:
2883-
// 12.2. Vector Single-Width Averaging Add and Subtract
2884-
case RISCV::VAADDU_VX:
2885-
case RISCV::VAADD_VX:
2886-
case RISCV::VASUBU_VX:
2887-
case RISCV::VASUB_VX:
2888-
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
2889-
case RISCV::VSMUL_VX:
2890-
// 16.1. Integer Scalar Move Instructions
2891-
case RISCV::VMV_S_X:
2892-
if (Bits < (1U << Log2SEW))
2893-
return false;
2894-
}
2895-
return true;
2782+
auto NumDemandedBits =
2783+
RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
2784+
return NumDemandedBits && Bits >= *NumDemandedBits;
28962785
}
28972786

28982787
// Return true if all users of this SDNode* only consume the lower \p Bits.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2847,3 +2847,115 @@ bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
28472847
MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
28482848
return FrmOp1.getImm() == FrmOp2.getImm();
28492849
}
2850+
2851+
std::optional<unsigned>
2852+
RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
2853+
// TODO: Handle Zvbb instructions
2854+
switch (Opcode) {
2855+
default:
2856+
return std::nullopt;
2857+
2858+
// 11.6. Vector Single-Width Shift Instructions
2859+
case RISCV::VSLL_VX:
2860+
case RISCV::VSRL_VX:
2861+
case RISCV::VSRA_VX:
2862+
// 12.4. Vector Single-Width Scaling Shift Instructions
2863+
case RISCV::VSSRL_VX:
2864+
case RISCV::VSSRA_VX:
2865+
// Only the low lg2(SEW) bits of the shift-amount value are used.
2866+
return Log2SEW;
2867+
2868+
// 11.7 Vector Narrowing Integer Right Shift Instructions
2869+
case RISCV::VNSRL_WX:
2870+
case RISCV::VNSRA_WX:
2871+
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
2872+
case RISCV::VNCLIPU_WX:
2873+
case RISCV::VNCLIP_WX:
2874+
// Only the low lg2(2*SEW) bits of the shift-amount value are used.
2875+
return Log2SEW + 1;
2876+
2877+
// 11.1. Vector Single-Width Integer Add and Subtract
2878+
case RISCV::VADD_VX:
2879+
case RISCV::VSUB_VX:
2880+
case RISCV::VRSUB_VX:
2881+
// 11.2. Vector Widening Integer Add/Subtract
2882+
case RISCV::VWADDU_VX:
2883+
case RISCV::VWSUBU_VX:
2884+
case RISCV::VWADD_VX:
2885+
case RISCV::VWSUB_VX:
2886+
case RISCV::VWADDU_WX:
2887+
case RISCV::VWSUBU_WX:
2888+
case RISCV::VWADD_WX:
2889+
case RISCV::VWSUB_WX:
2890+
// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2891+
case RISCV::VADC_VXM:
2892+
case RISCV::VADC_VIM:
2893+
case RISCV::VMADC_VXM:
2894+
case RISCV::VMADC_VIM:
2895+
case RISCV::VMADC_VX:
2896+
case RISCV::VSBC_VXM:
2897+
case RISCV::VMSBC_VXM:
2898+
case RISCV::VMSBC_VX:
2899+
// 11.5 Vector Bitwise Logical Instructions
2900+
case RISCV::VAND_VX:
2901+
case RISCV::VOR_VX:
2902+
case RISCV::VXOR_VX:
2903+
// 11.8. Vector Integer Compare Instructions
2904+
case RISCV::VMSEQ_VX:
2905+
case RISCV::VMSNE_VX:
2906+
case RISCV::VMSLTU_VX:
2907+
case RISCV::VMSLT_VX:
2908+
case RISCV::VMSLEU_VX:
2909+
case RISCV::VMSLE_VX:
2910+
case RISCV::VMSGTU_VX:
2911+
case RISCV::VMSGT_VX:
2912+
// 11.9. Vector Integer Min/Max Instructions
2913+
case RISCV::VMINU_VX:
2914+
case RISCV::VMIN_VX:
2915+
case RISCV::VMAXU_VX:
2916+
case RISCV::VMAX_VX:
2917+
// 11.10. Vector Single-Width Integer Multiply Instructions
2918+
case RISCV::VMUL_VX:
2919+
case RISCV::VMULH_VX:
2920+
case RISCV::VMULHU_VX:
2921+
case RISCV::VMULHSU_VX:
2922+
// 11.11. Vector Integer Divide Instructions
2923+
case RISCV::VDIVU_VX:
2924+
case RISCV::VDIV_VX:
2925+
case RISCV::VREMU_VX:
2926+
case RISCV::VREM_VX:
2927+
// 11.12. Vector Widening Integer Multiply Instructions
2928+
case RISCV::VWMUL_VX:
2929+
case RISCV::VWMULU_VX:
2930+
case RISCV::VWMULSU_VX:
2931+
// 11.13. Vector Single-Width Integer Multiply-Add Instructions
2932+
case RISCV::VMACC_VX:
2933+
case RISCV::VNMSAC_VX:
2934+
case RISCV::VMADD_VX:
2935+
case RISCV::VNMSUB_VX:
2936+
// 11.14. Vector Widening Integer Multiply-Add Instructions
2937+
case RISCV::VWMACCU_VX:
2938+
case RISCV::VWMACC_VX:
2939+
case RISCV::VWMACCSU_VX:
2940+
case RISCV::VWMACCUS_VX:
2941+
// 11.15. Vector Integer Merge Instructions
2942+
case RISCV::VMERGE_VXM:
2943+
// 11.16. Vector Integer Move Instructions
2944+
case RISCV::VMV_V_X:
2945+
// 12.1. Vector Single-Width Saturating Add and Subtract
2946+
case RISCV::VSADDU_VX:
2947+
case RISCV::VSADD_VX:
2948+
case RISCV::VSSUBU_VX:
2949+
case RISCV::VSSUB_VX:
2950+
// 12.2. Vector Single-Width Averaging Add and Subtract
2951+
case RISCV::VAADDU_VX:
2952+
case RISCV::VAADD_VX:
2953+
case RISCV::VASUBU_VX:
2954+
case RISCV::VASUB_VX:
2955+
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
2956+
case RISCV::VSMUL_VX:
2957+
// 16.1. Integer Scalar Move Instructions
2958+
case RISCV::VMV_S_X:
2959+
return 1U << Log2SEW;
2960+
}
2961+
}

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,12 @@ int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
265265
// one of the instructions does not have rounding mode, false will be returned.
266266
bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
267267

268+
// If \p Opcode is a .vx vector instruction, returns the lower number of bits
269+
// that are used from the scalar .x operand for a given \p Log2SEW. Otherwise
270+
// returns null.
271+
std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
272+
unsigned Log2SEW);
273+
268274
// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
269275
static constexpr int64_t VLMaxSentinel = -1LL;
270276

‎llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Lines changed: 4 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
8888
return false;
8989

9090
const MCInstrDesc &MCID = MI.getDesc();
91-
const uint64_t TSFlags = MI.getDesc().TSFlags;
91+
const uint64_t TSFlags = MCID.TSFlags;
9292
if (!RISCVII::hasSEWOp(TSFlags))
9393
return false;
9494
assert(RISCVII::hasVLOp(TSFlags));
@@ -97,120 +97,9 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
9797
if (UserOp.getOperandNo() == RISCVII::getVLOpNum(MCID))
9898
return false;
9999

100-
// TODO: Handle Zvbb instructions
101-
switch (PseudoInfo->BaseInstr) {
102-
default:
103-
return false;
104-
105-
// 11.6. Vector Single-Width Shift Instructions
106-
case RISCV::VSLL_VX:
107-
case RISCV::VSRL_VX:
108-
case RISCV::VSRA_VX:
109-
// 12.4. Vector Single-Width Scaling Shift Instructions
110-
case RISCV::VSSRL_VX:
111-
case RISCV::VSSRA_VX:
112-
// Only the low lg2(SEW) bits of the shift-amount value are used.
113-
if (Bits < Log2SEW)
114-
return false;
115-
break;
116-
117-
// 11.7 Vector Narrowing Integer Right Shift Instructions
118-
case RISCV::VNSRL_WX:
119-
case RISCV::VNSRA_WX:
120-
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
121-
case RISCV::VNCLIPU_WX:
122-
case RISCV::VNCLIP_WX:
123-
// Only the low lg2(2*SEW) bits of the shift-amount value are used.
124-
if (Bits < Log2SEW + 1)
125-
return false;
126-
break;
127-
128-
// 11.1. Vector Single-Width Integer Add and Subtract
129-
case RISCV::VADD_VX:
130-
case RISCV::VSUB_VX:
131-
case RISCV::VRSUB_VX:
132-
// 11.2. Vector Widening Integer Add/Subtract
133-
case RISCV::VWADDU_VX:
134-
case RISCV::VWSUBU_VX:
135-
case RISCV::VWADD_VX:
136-
case RISCV::VWSUB_VX:
137-
case RISCV::VWADDU_WX:
138-
case RISCV::VWSUBU_WX:
139-
case RISCV::VWADD_WX:
140-
case RISCV::VWSUB_WX:
141-
// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
142-
case RISCV::VADC_VXM:
143-
case RISCV::VADC_VIM:
144-
case RISCV::VMADC_VXM:
145-
case RISCV::VMADC_VIM:
146-
case RISCV::VMADC_VX:
147-
case RISCV::VSBC_VXM:
148-
case RISCV::VMSBC_VXM:
149-
case RISCV::VMSBC_VX:
150-
// 11.5 Vector Bitwise Logical Instructions
151-
case RISCV::VAND_VX:
152-
case RISCV::VOR_VX:
153-
case RISCV::VXOR_VX:
154-
// 11.8. Vector Integer Compare Instructions
155-
case RISCV::VMSEQ_VX:
156-
case RISCV::VMSNE_VX:
157-
case RISCV::VMSLTU_VX:
158-
case RISCV::VMSLT_VX:
159-
case RISCV::VMSLEU_VX:
160-
case RISCV::VMSLE_VX:
161-
case RISCV::VMSGTU_VX:
162-
case RISCV::VMSGT_VX:
163-
// 11.9. Vector Integer Min/Max Instructions
164-
case RISCV::VMINU_VX:
165-
case RISCV::VMIN_VX:
166-
case RISCV::VMAXU_VX:
167-
case RISCV::VMAX_VX:
168-
// 11.10. Vector Single-Width Integer Multiply Instructions
169-
case RISCV::VMUL_VX:
170-
case RISCV::VMULH_VX:
171-
case RISCV::VMULHU_VX:
172-
case RISCV::VMULHSU_VX:
173-
// 11.11. Vector Integer Divide Instructions
174-
case RISCV::VDIVU_VX:
175-
case RISCV::VDIV_VX:
176-
case RISCV::VREMU_VX:
177-
case RISCV::VREM_VX:
178-
// 11.12. Vector Widening Integer Multiply Instructions
179-
case RISCV::VWMUL_VX:
180-
case RISCV::VWMULU_VX:
181-
case RISCV::VWMULSU_VX:
182-
// 11.13. Vector Single-Width Integer Multiply-Add Instructions
183-
case RISCV::VMACC_VX:
184-
case RISCV::VNMSAC_VX:
185-
case RISCV::VMADD_VX:
186-
case RISCV::VNMSUB_VX:
187-
// 11.14. Vector Widening Integer Multiply-Add Instructions
188-
case RISCV::VWMACCU_VX:
189-
case RISCV::VWMACC_VX:
190-
case RISCV::VWMACCSU_VX:
191-
case RISCV::VWMACCUS_VX:
192-
// 11.15. Vector Integer Merge Instructions
193-
case RISCV::VMERGE_VXM:
194-
// 11.16. Vector Integer Move Instructions
195-
case RISCV::VMV_V_X:
196-
// 12.1. Vector Single-Width Saturating Add and Subtract
197-
case RISCV::VSADDU_VX:
198-
case RISCV::VSADD_VX:
199-
case RISCV::VSSUBU_VX:
200-
case RISCV::VSSUB_VX:
201-
// 12.2. Vector Single-Width Averaging Add and Subtract
202-
case RISCV::VAADDU_VX:
203-
case RISCV::VAADD_VX:
204-
case RISCV::VASUBU_VX:
205-
case RISCV::VASUB_VX:
206-
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
207-
case RISCV::VSMUL_VX:
208-
// 16.1. Integer Scalar Move Instructions
209-
case RISCV::VMV_S_X:
210-
if (Bits < (1U << Log2SEW))
211-
return false;
212-
}
213-
return true;
100+
auto NumDemandedBits =
101+
RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
102+
return NumDemandedBits && Bits >= *NumDemandedBits;
214103
}
215104

216105
// Checks if all users only demand the lower \p OrigBits of the original

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