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[AMDGPU][AsmParser] Do not use predicates for validation of NamedIntOperands. (llvm#90251)
Their job is to discriminate between different types of operands, not to check if they are valid. For validation we can use conversion functions. Clears the road to generating predicates automatically. Part of <llvm#62629>.
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-37
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5 files changed

+45
-37
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 9 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -385,8 +385,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
385385
bool isIdxen() const { return isImmTy(ImmTyIdxen); }
386386
bool isAddr64() const { return isImmTy(ImmTyAddr64); }
387387
bool isOffset() const { return isImmTy(ImmTyOffset); }
388-
bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
389-
bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
388+
bool isOffset0() const { return isImmTy(ImmTyOffset0); }
389+
bool isOffset1() const { return isImmTy(ImmTyOffset1); }
390390
bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }
391391
bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); }
392392
bool isGDS() const { return isImmTy(ImmTyGDS); }
@@ -411,9 +411,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
411411
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
412412
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
413413
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
414-
bool isByteSel() const {
415-
return isImmTy(ImmTyByteSel) && isUInt<2>(getImm());
416-
}
414+
bool isByteSel() const { return isImmTy(ImmTyByteSel); }
417415

418416
bool isRegOrImm() const {
419417
return isReg() || isImm();
@@ -8939,11 +8937,11 @@ bool AMDGPUOperand::isBLGP() const {
89398937
}
89408938

89418939
bool AMDGPUOperand::isCBSZ() const {
8942-
return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());
8940+
return isImm() && getImmTy() == ImmTyCBSZ;
89438941
}
89448942

89458943
bool AMDGPUOperand::isABID() const {
8946-
return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());
8944+
return isImm() && getImmTy() == ImmTyABID;
89478945
}
89488946

89498947
bool AMDGPUOperand::isS16Imm() const {
@@ -9670,25 +9668,17 @@ bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
96709668
// LDSDIR
96719669
//===----------------------------------------------------------------------===//
96729670

9673-
bool AMDGPUOperand::isWaitVDST() const {
9674-
return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
9675-
}
9671+
bool AMDGPUOperand::isWaitVDST() const { return isImmTy(ImmTyWaitVDST); }
96769672

9677-
bool AMDGPUOperand::isWaitVAVDst() const {
9678-
return isImmTy(ImmTyWaitVAVDst) && isUInt<4>(getImm());
9679-
}
9673+
bool AMDGPUOperand::isWaitVAVDst() const { return isImmTy(ImmTyWaitVAVDst); }
96809674

9681-
bool AMDGPUOperand::isWaitVMVSrc() const {
9682-
return isImmTy(ImmTyWaitVMVSrc) && isUInt<1>(getImm());
9683-
}
9675+
bool AMDGPUOperand::isWaitVMVSrc() const { return isImmTy(ImmTyWaitVMVSrc); }
96849676

96859677
//===----------------------------------------------------------------------===//
96869678
// VINTERP
96879679
//===----------------------------------------------------------------------===//
96889680

9689-
bool AMDGPUOperand::isWaitEXP() const {
9690-
return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());
9691-
}
9681+
bool AMDGPUOperand::isWaitEXP() const { return isImmTy(ImmTyWaitEXP); }
96929682

96939683
//===----------------------------------------------------------------------===//
96949684
// Split Barrier

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 29 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,8 +1000,10 @@ def SDWAVopcDst : BoolRC {
10001000
}
10011001

10021002
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
1003-
string name = NAME, string ConvertMethod = "nullptr">
1003+
string name = NAME>
10041004
: CustomOperand<Type, Optional, name> {
1005+
string Validator = "[](int64_t V) { return true; }";
1006+
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
10051007
let ParserMethod =
10061008
"[this](OperandVector &Operands) -> ParseStatus { "#
10071009
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
@@ -1045,8 +1047,10 @@ class ArrayOperand0<string Id, string Name = NAME>
10451047
let ImmTy = "ImmTyOffset" in
10461048
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
10471049
def Offset : NamedIntOperand<i32, "offset">;
1050+
let Validator = "isUInt<8>" in {
10481051
def Offset0 : NamedIntOperand<i8, "offset0">;
10491052
def Offset1 : NamedIntOperand<i8, "offset1">;
1053+
}
10501054

10511055
def gds : NamedBitOperand<"gds", "GDS">;
10521056

@@ -1103,27 +1107,41 @@ let DefaultValue = "0xf" in {
11031107
def DppRowMask : NamedIntOperand<i32, "row_mask">;
11041108
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
11051109
}
1106-
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl", 1, "DppBoundCtrl",
1107-
"[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }">;
1110+
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
1111+
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
1112+
}
11081113

11091114
let DecoderMethod = "decodeDpp8FI" in
11101115
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
11111116
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
11121117

11131118
def blgp : CustomOperand<i32, 1, "BLGP">;
1114-
def CBSZ : NamedIntOperand<i32, "cbsz">;
1115-
def ABID : NamedIntOperand<i32, "abid">;
1116-
1119+
def CBSZ : NamedIntOperand<i32, "cbsz"> {
1120+
let Validator = "isUInt<3>";
1121+
}
1122+
def ABID : NamedIntOperand<i32, "abid"> {
1123+
let Validator = "isUInt<4>";
1124+
}
11171125
def hwreg : CustomOperand<i32, 0, "Hwreg">;
11181126

11191127
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
11201128

1121-
def WaitVDST : NamedIntOperand<i8, "wait_vdst">;
1122-
def WaitEXP : NamedIntOperand<i8, "wait_exp">;
1123-
def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst">;
1124-
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc">;
1129+
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
1130+
let Validator = "isUInt<4>";
1131+
}
1132+
def WaitEXP : NamedIntOperand<i8, "wait_exp"> {
1133+
let Validator = "isUInt<3>";
1134+
}
1135+
def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
1136+
let Validator = "isUInt<4>";
1137+
}
1138+
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
1139+
let Validator = "isUInt<1>";
1140+
}
11251141

1126-
def ByteSel : NamedIntOperand<i8, "byte_sel">;
1142+
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
1143+
let Validator = "isUInt<2>";
1144+
}
11271145

11281146
class KImmFPOperand<ValueType vt> : ImmOperand<vt> {
11291147
let OperandNamespace = "AMDGPU";

‎llvm/test/MC/AMDGPU/ds-err.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,19 +18,19 @@ ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
1818
ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
1919

2020
// offset0 too big
21-
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
21+
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value.
2222
ds_write2_b32 v2, v4, v6 offset0:1000000000
2323

2424
// offset0 too big
25-
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
25+
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value.
2626
ds_write2_b32 v2, v4, v6 offset0:0x100
2727

2828
// offset1 too big
29-
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
29+
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value.
3030
ds_write2_b32 v2, v4, v6 offset1:1000000000
3131

3232
// offset1 too big
33-
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
33+
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value.
3434
ds_write2_b32 v2, v4, v6 offset1:0x100
3535

3636
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AMDGPU/gfx11_asm_err.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,13 +22,13 @@ s_delay_alu instid0(VALU_DEP_1) | SALU_CYCLE_1)
2222
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
2323

2424
lds_direct_load v15 wait_vdst:16
25-
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
25+
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_vdst value.
2626

2727
lds_direct_load v15 wait_vdst
2828
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
2929

3030
v_interp_p10_f32 v0, v1, v2, v3 wait_exp:8
31-
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31+
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_exp value.
3232

3333
v_interp_p2_f32 v0, -v1, v2, v3 wait_exp
3434
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,6 @@ v_permlane16_var_b32 v5, v1, v2 op_sel:[0, 0, 1]
103103
// GFX12-NEXT:{{^}} ^
104104

105105
v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4
106-
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
106+
// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid byte_sel value.
107107
// GFX12-NEXT:{{^}}v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4
108108
// GFX12-NEXT:{{^}} ^

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