Skip to content

Commit e8ce76f

Browse files
authored
[GlobalISel][AArch64] Allow vector ptr to int unmerges (llvm#115228)
Vector pointer -> scalar integer unmerges are already legal. This loosens the verifier check for vector-of-pointers -> vectors.
1 parent 5005f8d commit e8ce76f

File tree

2 files changed

+24
-1
lines changed

2 files changed

+24
-1
lines changed

llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1487,7 +1487,9 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
14871487
LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
14881488
if (DstTy.isVector()) {
14891489
// This case is the converse of G_CONCAT_VECTORS.
1490-
if (!SrcTy.isVector() || SrcTy.getScalarType() != DstTy.getScalarType() ||
1490+
if (!SrcTy.isVector() ||
1491+
(SrcTy.getScalarType() != DstTy.getScalarType() &&
1492+
!SrcTy.isPointerVector()) ||
14911493
SrcTy.isScalableVector() != DstTy.isScalableVector() ||
14921494
SrcTy.getSizeInBits() != NumDsts * DstTy.getSizeInBits())
14931495
report("G_UNMERGE_VALUES source operand does not match vector "

llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -145,3 +145,24 @@ entry:
145145
%0 = getelementptr inbounds [8 x i32], ptr @arr, i64 0, <2 x i64> %offs
146146
ret <2 x ptr> %0
147147
}
148+
149+
define <4 x ptr> @vector_gep_v4i32(<4 x ptr> %b, <4 x i32> %off) {
150+
; CHECK-LABEL: name: vector_gep_v4i32
151+
; CHECK: bb.1.entry:
152+
; CHECK-NEXT: liveins: $q0, $q1, $q2
153+
; CHECK-NEXT: {{ $}}
154+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
155+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
156+
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x p0>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>)
157+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
158+
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s64>) = G_SEXT [[COPY2]](<4 x s32>)
159+
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(<4 x p0>) = G_PTR_ADD [[CONCAT_VECTORS]], [[SEXT]](<4 x s64>)
160+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x p0>) = COPY [[PTR_ADD]](<4 x p0>)
161+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[COPY3]](<4 x p0>)
162+
; CHECK-NEXT: $q0 = COPY [[UV]](<2 x s64>)
163+
; CHECK-NEXT: $q1 = COPY [[UV1]](<2 x s64>)
164+
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
165+
entry:
166+
%g = getelementptr i8, <4 x ptr> %b, <4 x i32> %off
167+
ret <4 x ptr> %g
168+
}

0 commit comments

Comments
 (0)