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[AArch64][FMV] Add rcpc3 support, introduce bits for features extensi… (llvm#68104)
…on and initialization. The patch implements FEAT_LRCPC3 support (Load-Acquire RCpc instructions version 3) in Function Multi Versioning. To maintain compatibility while features list grows extension bit FEAT_EXT and initialization bit FEAT_INIT are reserved.
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4 files changed

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-54
lines changed

4 files changed

+58
-54
lines changed

‎clang/test/CodeGen/attr-target-version.c

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { re
3535
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
3636
inline int __attribute__((target_version("sve2+sve2-pmull128+sve2-bitperm"))) fmv_inline(void) { return 9; }
3737
inline int __attribute__((target_version("sve2-sm4+memtag2"))) fmv_inline(void) { return 10; }
38-
inline int __attribute__((target_version("memtag3"))) fmv_inline(void) { return 11; }
38+
inline int __attribute__((target_version("memtag3+rcpc3"))) fmv_inline(void) { return 11; }
3939
inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; }
4040

4141
__attribute__((target_version("ls64"))) int fmv_e(void);
@@ -289,68 +289,68 @@ int hoo(void) {
289289
// CHECK-NEXT: ret ptr @fmv_inline._Msha3Mi8mmMf32mm
290290
// CHECK: resolver_else6:
291291
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
292-
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 19791209299968
293-
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 19791209299968
292+
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 288265560523800576
293+
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 288265560523800576
294294
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
295295
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
296296
// CHECK: resolver_return7:
297-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-sm4Mmemtag2
297+
// CHECK-NEXT: ret ptr @fmv_inline._Mrcpc3Mmemtag3
298298
// CHECK: resolver_else8:
299299
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
300-
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 1236950581248
301-
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 1236950581248
300+
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
301+
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
302302
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
303303
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
304304
// CHECK: resolver_return9:
305-
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
305+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-sm4Mmemtag2
306306
// CHECK: resolver_else10:
307307
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
308-
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4295098368
309-
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4295098368
308+
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248
309+
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1236950581248
310310
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
311311
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
312312
// CHECK: resolver_return11:
313-
// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16
313+
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
314314
// CHECK: resolver_else12:
315315
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
316-
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 3221225472
317-
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 3221225472
316+
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368
317+
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368
318318
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
319319
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
320320
// CHECK: resolver_return13:
321-
// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16
321+
// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16
322322
// CHECK: resolver_else14:
323323
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
324-
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 20971520
325-
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 20971520
324+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472
325+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472
326326
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
327327
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
328328
// CHECK: resolver_return15:
329-
// CHECK-NEXT: ret ptr @fmv_inline._MrcpcMfrintts
329+
// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16
330330
// CHECK: resolver_else16:
331331
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
332-
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 8650752
333-
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 8650752
332+
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
333+
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971520
334334
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
335335
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
336336
// CHECK: resolver_return17:
337-
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
337+
// CHECK-NEXT: ret ptr @fmv_inline._MrcpcMfrintts
338338
// CHECK: resolver_else18:
339339
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
340-
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 1572864
341-
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 1572864
340+
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
341+
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 8650752
342342
// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]
343343
// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
344344
// CHECK: resolver_return19:
345-
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
345+
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
346346
// CHECK: resolver_else20:
347347
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
348-
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 35184372088832
349-
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 35184372088832
348+
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1572864
349+
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1572864
350350
// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]
351351
// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
352352
// CHECK: resolver_return21:
353-
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3
353+
// CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt
354354
// CHECK: resolver_else22:
355355
// CHECK-NEXT: ret ptr @fmv_inline
356356
// CHECK-LABEL: @fmv_e.resolver(
@@ -437,7 +437,7 @@ int hoo(void) {
437437
// CHECK-LABEL: @fmv_inline._Msve2-sm4Mmemtag2(
438438
// CHECK-NEXT: entry:
439439
// CHECK-NEXT: ret i32 10
440-
// CHECK-LABEL: @fmv_inline._Mmemtag3(
440+
// CHECK-LABEL: @fmv_inline._Mrcpc3Mmemtag3(
441441
// CHECK-NEXT: entry:
442442
// CHECK-NEXT: ret i32 11
443443
// CHECK-LABEL: @fmv_inline(
@@ -534,7 +534,7 @@ int hoo(void) {
534534
// CHECK: attributes #20 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3" }
535535
// CHECK: attributes #21 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm" }
536536
// CHECK: attributes #22 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+ls64,+mte,+neon,+sve,+sve2,+sve2-sm4" }
537-
// CHECK: attributes #23 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+mte" }
537+
// CHECK: attributes #23 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+mte,+rcpc,+rcpc3" }
538538
// CHECK: attributes #24 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+ls64,+sb" }
539539

540540
// CHECK-NOFMV: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }

‎clang/test/Sema/attr-target-clones-aarch64.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang_cc1 -triple aarch64-linux-gnu -fsyntax-only -verify %s
22

3-
void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3"))) no_def(void);
3+
void __attribute__((target_clones("fp16+sve2-aes", "sb+sve2-sha3+rcpc3"))) no_def(void);
44

55
// expected-warning@+1 {{unsupported 'default' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
66
void __attribute__((target_clones("default+sha3"))) warn1(void);

‎clang/test/SemaCXX/attr-target-version.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ void __attribute__((target_version("vmull"))) wrong_tv(void);
55

66
void __attribute__((target_version("dotprod"))) no_def(void);
77
void __attribute__((target_version("rdm+fp"))) no_def(void);
8+
void __attribute__((target_version("rcpc3"))) no_def(void);
89

910
// expected-error@+1 {{no matching function for call to 'no_def'}}
1011
void foo(void) { no_def(); }

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 29 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -87,11 +87,14 @@ enum CPUFeatures {
8787
FEAT_SME_F64,
8888
FEAT_SME_I64,
8989
FEAT_SME2,
90-
FEAT_MAX
90+
FEAT_RCPC3,
91+
FEAT_MAX,
92+
FEAT_EXT = 62,
93+
FEAT_INIT
9194
};
9295

93-
static_assert(FEAT_MAX <= 64,
94-
"CPUFeatures enum must not have more than 64 entries");
96+
static_assert(FEAT_MAX < 62,
97+
"Number of features in CPUFeatures are limited to 62 entries");
9598

9699
// Arch extension modifiers for CPUs. These are labelled with their Arm ARM
97100
// feature name (though the canonical reference for those is AArch64.td)
@@ -181,14 +184,14 @@ struct ExtensionInfo {
181184
// clang-format off
182185
inline constexpr ExtensionInfo Extensions[] = {
183186
{"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon", 150},
184-
{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_MAX, "", 0},
187+
{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
185188
{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
186-
{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_MAX, "", 0},
189+
{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
187190
{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
188191
{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
189-
{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_MAX, "+aes,+sha2", 0},
190-
{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_MAX, "", 0},
191-
{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_MAX, "", 0},
192+
{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT, "+aes,+sha2", 0},
193+
{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
194+
{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
192195
{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
193196
{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
194197
{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 50},
@@ -204,30 +207,30 @@ inline constexpr ExtensionInfo Extensions[] = {
204207
{"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16, "+fullfp16,+fp-armv8,+neon", 170},
205208
{"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML, "+fp16fml,+fullfp16,+fp-armv8,+neon", 40},
206209
{"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
207-
{"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_MAX, "", 0},
210+
{"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0},
208211
{"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
209-
{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_MAX, "", 0},
212+
{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_INIT, "", 0},
210213
{"jscvt", AArch64::AEK_NONE, {}, {}, FEAT_JSCVT, "+fp-armv8,+neon,+jsconv", 210},
211214
{"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 540},
212215
{"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
213216
{"ls64", AArch64::AEK_LS64, "+ls64", "-ls64", FEAT_LS64, "", 520},
214217
{"lse", AArch64::AEK_LSE, "+lse", "-lse", FEAT_LSE, "+lse", 80},
215-
{"lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", FEAT_MAX, "", 0},
218+
{"lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", FEAT_INIT, "", 0},
216219
{"memtag", AArch64::AEK_MTE, "+mte", "-mte", FEAT_MEMTAG, "", 440},
217220
{"memtag2", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG2, "+mte", 450},
218221
{"memtag3", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG3, "+mte", 460},
219-
{"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_MAX, "", 0},
220-
{"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_MAX, "", 0},
222+
{"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_INIT, "", 0},
223+
{"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_INIT, "", 0},
221224
{"pmull", AArch64::AEK_NONE, {}, {}, FEAT_PMULL, "+aes,+fp-armv8,+neon", 160},
222-
{"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_MAX, "", 0},
225+
{"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_INIT, "", 0},
223226
{"predres", AArch64::AEK_PREDRES, "+predres", "-predres", FEAT_PREDRES, "+predres", 480},
224-
{"predres2", AArch64::AEK_SPECRES2, "+specres2", "-specres2", FEAT_MAX, "", 0},
225-
{"profile", AArch64::AEK_PROFILE, "+spe", "-spe", FEAT_MAX, "", 0},
226-
{"ras", AArch64::AEK_RAS, "+ras", "-ras", FEAT_MAX, "", 0},
227-
{"rasv2", AArch64::AEK_RASv2, "+rasv2", "-rasv2", FEAT_MAX, "", 0},
227+
{"predres2", AArch64::AEK_SPECRES2, "+specres2", "-specres2", FEAT_INIT, "", 0},
228+
{"profile", AArch64::AEK_PROFILE, "+spe", "-spe", FEAT_INIT, "", 0},
229+
{"ras", AArch64::AEK_RAS, "+ras", "-ras", FEAT_INIT, "", 0},
230+
{"rasv2", AArch64::AEK_RASv2, "+rasv2", "-rasv2", FEAT_INIT, "", 0},
228231
{"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230},
229232
{"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240},
230-
{"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_MAX, "", 0},
233+
{"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3, "+rcpc,+rcpc3", 241},
231234
{"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM, "+rdm,+fp-armv8,+neon", 70},
232235
{"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10},
233236
{"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300},
@@ -237,12 +240,12 @@ inline constexpr ExtensionInfo Extensions[] = {
237240
{"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140},
238241
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100},
239242
{"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 60},
240-
{"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_MAX, "", 0},
243+
{"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "", 0},
241244
{"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560},
242245
{"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},
243246
{"sme", AArch64::AEK_SME, "+sme", "-sme", FEAT_SME, "+sme,+bf16", 430},
244247
{"sme2", AArch64::AEK_SME2, "+sme2", "-sme2", FEAT_SME2, "+sme2,+sme,+bf16", 580},
245-
{"sme2p1", AArch64::AEK_SME2p1, "+sme2p1", "-sme2p1", FEAT_MAX, "", 0},
248+
{"sme2p1", AArch64::AEK_SME2p1, "+sme2p1", "-sme2p1", FEAT_INIT, "", 0},
246249
{"ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs", FEAT_SSBS, "", 490},
247250
{"ssbs2", AArch64::AEK_NONE, {}, {}, FEAT_SSBS2, "+ssbs", 500},
248251
{"sve-bf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_BF16, "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320},
@@ -255,13 +258,13 @@ inline constexpr ExtensionInfo Extensions[] = {
255258
{"sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3", FEAT_SVE_SHA3, "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410},
256259
{"sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4", FEAT_SVE_SM4, "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420},
257260
{"sve2", AArch64::AEK_SVE2, "+sve2", "-sve2", FEAT_SVE2, "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370},
258-
{"sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1", FEAT_MAX, "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon", 0},
259-
{"the", AArch64::AEK_THE, "+the", "-the", FEAT_MAX, "", 0},
260-
{"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_MAX, "", 0},
261+
{"sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1", FEAT_INIT, "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon", 0},
262+
{"the", AArch64::AEK_THE, "+the", "-the", FEAT_INIT, "", 0},
263+
{"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_INIT, "", 0},
261264
{"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550},
262-
{"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_MAX, "", 0},
265+
{"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_INIT, "", 0},
263266
// Special cases
264-
{"none", AArch64::AEK_NONE, {}, {}, FEAT_MAX, "", ExtensionInfo::MaxFMVPriority},
267+
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
265268
};
266269
// clang-format on
267270

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