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Chen Zheng
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[PowerPC] make expensive mflr be away from its user in the function prologue
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
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136 files changed

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‎llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Lines changed: 26 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -616,6 +616,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
616616
// AIX assembler does not support cfi directives.
617617
const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
618618

619+
const bool HasFastMFLR = Subtarget.hasFastMFLR();
620+
619621
// Get processor type.
620622
bool isPPC64 = Subtarget.isPPC64();
621623
// Get the ABI.
@@ -837,10 +839,11 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
837839
// Generate the instruction to store the LR. In the case where ROP protection
838840
// is required the register holding the LR should not be killed as it will be
839841
// used by the hash store instruction.
840-
if (MustSaveLR) {
842+
auto SaveLR = [&](int64_t Offset) {
843+
assert(MustSaveLR && "LR is not required to be saved!");
841844
BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
842845
.addReg(ScratchReg, getKillRegState(!HasROPProtect))
843-
.addImm(LROffset)
846+
.addImm(Offset)
844847
.addReg(SPReg);
845848

846849
// Add the ROP protection Hash Store instruction.
@@ -861,7 +864,10 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
861864
.addImm(ImmOffset)
862865
.addReg(SPReg);
863866
}
864-
}
867+
};
868+
869+
if (MustSaveLR && HasFastMFLR)
870+
SaveLR(LROffset);
865871

866872
if (MustSaveCR &&
867873
!(SingleScratchReg && MustSaveLR)) {
@@ -873,8 +879,11 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
873879
}
874880

875881
// Skip the rest if this is a leaf function & all spills fit in the Red Zone.
876-
if (!FrameSize)
882+
if (!FrameSize) {
883+
if (MustSaveLR && !HasFastMFLR)
884+
SaveLR(LROffset);
877885
return;
886+
}
878887

879888
// Adjust stack pointer: r1 += NegFrameSize.
880889
// If there is a preferred stack alignment, align R1 now
@@ -888,7 +897,15 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
888897

889898
// Have we generated a STUX instruction to claim stack frame? If so,
890899
// the negated frame size will be placed in ScratchReg.
891-
bool HasSTUX = false;
900+
bool HasSTUX =
901+
(TLI.hasInlineStackProbe(MF) && FrameSize > TLI.getStackProbeSize(MF)) ||
902+
(HasBP && MaxAlign > 1) || isLargeFrame;
903+
904+
// If we use STUX to update the stack pointer, we need the two scratch
905+
// registers TempReg and ScratchReg, we have to save LR here which is stored
906+
// in ScratchReg.
907+
if (HasSTUX && MustSaveLR && !HasFastMFLR)
908+
SaveLR(LROffset);
892909

893910
// If FrameSize <= TLI.getStackProbeSize(MF), as POWER ABI requires backchain
894911
// pointer is always stored at SP, we will get a free probe due to an essential
@@ -909,7 +926,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
909926
BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
910927
.addReg(ScratchReg)
911928
.addReg(SPReg);
912-
HasSTUX = true;
913929
}
914930
} else {
915931
// This condition must be kept in sync with canUseAsPrologue.
@@ -941,21 +957,17 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
941957
.addReg(SPReg, RegState::Kill)
942958
.addReg(SPReg)
943959
.addReg(ScratchReg);
944-
HasSTUX = true;
945-
946960
} else if (!isLargeFrame) {
947961
BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
948962
.addReg(SPReg)
949963
.addImm(NegFrameSize)
950964
.addReg(SPReg);
951-
952965
} else {
953966
TII.materializeImmPostRA(MBB, MBBI, dl, ScratchReg, NegFrameSize);
954967
BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
955968
.addReg(SPReg, RegState::Kill)
956969
.addReg(SPReg)
957970
.addReg(ScratchReg);
958-
HasSTUX = true;
959971
}
960972
}
961973

@@ -1082,6 +1094,10 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
10821094
}
10831095
}
10841096

1097+
// Save the LR now.
1098+
if (!HasSTUX && MustSaveLR && !HasFastMFLR)
1099+
SaveLR(LROffset + FrameSize);
1100+
10851101
// Add Call Frame Information for the instructions we generated above.
10861102
if (needsCFI) {
10871103
unsigned CFIIndex;

‎llvm/test/CodeGen/PowerPC/2007-09-08-unaligned.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,8 @@ define i32 @main() {
5454
; CHECK-LABEL: main:
5555
; CHECK: # %bb.0: # %entry
5656
; CHECK-NEXT: mflr 0
57-
; CHECK-NEXT: stw 0, 4(1)
5857
; CHECK-NEXT: stwu 1, -16(1)
58+
; CHECK-NEXT: stw 0, 20(1)
5959
; CHECK-NEXT: .cfi_def_cfa_offset 16
6060
; CHECK-NEXT: .cfi_offset lr, 4
6161
; CHECK-NEXT: bl foo

‎llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,8 @@ define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) personality ptr @__
1010
; CHECK: # %bb.0: # %entry
1111
; CHECK-NEXT: mflr 0
1212
; CHECK-NEXT: std 31, -8(1)
13-
; CHECK-NEXT: std 0, 16(1)
1413
; CHECK-NEXT: stdu 1, -176(1)
14+
; CHECK-NEXT: std 0, 192(1)
1515
; CHECK-NEXT: .cfi_def_cfa_offset 176
1616
; CHECK-NEXT: .cfi_offset r31, -8
1717
; CHECK-NEXT: .cfi_offset lr, 16

‎llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
55
; CHECK-LABEL: __fixunstfdi:
66
; CHECK: # %bb.0: # %entry
77
; CHECK-NEXT: mflr 0
8-
; CHECK-NEXT: stw 0, 4(1)
98
; CHECK-NEXT: stwu 1, -464(1)
109
; CHECK-NEXT: mfcr 12
11-
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
10+
; CHECK-NEXT: stw 0, 468(1)
1211
; CHECK-NEXT: lis 3, .LCPI0_0@ha
12+
; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
1313
; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
1414
; CHECK-NEXT: stw 12, 408(1)
1515
; CHECK-NEXT: stfd 2, 376(1)

‎llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@ define ptr @g() nounwind readnone {
2020
; CHECK-LABEL: g:
2121
; CHECK: # %bb.0: # %entry
2222
; CHECK-NEXT: mflr 0
23-
; CHECK-NEXT: stw 0, 4(1)
2423
; CHECK-NEXT: stwu 1, -16(1)
24+
; CHECK-NEXT: stw 0, 20(1)
2525
; CHECK-NEXT: lwz 3, 0(1)
2626
; CHECK-NEXT: lwz 3, 0(3)
2727
; CHECK-NEXT: lwz 3, 4(3)

‎llvm/test/CodeGen/PowerPC/CSR-fit.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,11 @@ define dso_local signext i32 @caller1(i32 signext %a, i32 signext %b) local_unna
1717
; CHECK-PWR8-NEXT: .cfi_offset r15, -136
1818
; CHECK-PWR8-NEXT: std r14, -144(r1) # 8-byte Folded Spill
1919
; CHECK-PWR8-NEXT: std r15, -136(r1) # 8-byte Folded Spill
20-
; CHECK-PWR8-NEXT: std r0, 16(r1)
2120
; CHECK-PWR8-NEXT: stdu r1, -176(r1)
2221
; CHECK-PWR8-NEXT: #APP
2322
; CHECK-PWR8-NEXT: add r3, r3, r4
2423
; CHECK-PWR8-NEXT: #NO_APP
24+
; CHECK-PWR8-NEXT: std r0, 192(r1)
2525
; CHECK-PWR8-NEXT: extsw r3, r3
2626
; CHECK-PWR8-NEXT: bl callee
2727
; CHECK-PWR8-NEXT: nop
@@ -41,12 +41,12 @@ define dso_local signext i32 @caller1(i32 signext %a, i32 signext %b) local_unna
4141
; CHECK-PWR9-NEXT: .cfi_offset r15, -136
4242
; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill
4343
; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill
44-
; CHECK-PWR9-NEXT: std r0, 16(r1)
4544
; CHECK-PWR9-NEXT: stdu r1, -176(r1)
4645
; CHECK-PWR9-NEXT: #APP
4746
; CHECK-PWR9-NEXT: add r3, r3, r4
4847
; CHECK-PWR9-NEXT: #NO_APP
4948
; CHECK-PWR9-NEXT: extsw r3, r3
49+
; CHECK-PWR9-NEXT: std r0, 192(r1)
5050
; CHECK-PWR9-NEXT: bl callee
5151
; CHECK-PWR9-NEXT: nop
5252
; CHECK-PWR9-NEXT: addi r1, r1, 176
@@ -71,11 +71,11 @@ define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unna
7171
; CHECK-PWR8-NEXT: .cfi_offset f15, -136
7272
; CHECK-PWR8-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
7373
; CHECK-PWR8-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
74-
; CHECK-PWR8-NEXT: std r0, 16(r1)
7574
; CHECK-PWR8-NEXT: stdu r1, -176(r1)
7675
; CHECK-PWR8-NEXT: #APP
7776
; CHECK-PWR8-NEXT: add r3, r3, r4
7877
; CHECK-PWR8-NEXT: #NO_APP
78+
; CHECK-PWR8-NEXT: std r0, 192(r1)
7979
; CHECK-PWR8-NEXT: extsw r3, r3
8080
; CHECK-PWR8-NEXT: bl callee
8181
; CHECK-PWR8-NEXT: nop
@@ -95,12 +95,12 @@ define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unna
9595
; CHECK-PWR9-NEXT: .cfi_offset f15, -136
9696
; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
9797
; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
98-
; CHECK-PWR9-NEXT: std r0, 16(r1)
9998
; CHECK-PWR9-NEXT: stdu r1, -176(r1)
10099
; CHECK-PWR9-NEXT: #APP
101100
; CHECK-PWR9-NEXT: add r3, r3, r4
102101
; CHECK-PWR9-NEXT: #NO_APP
103102
; CHECK-PWR9-NEXT: extsw r3, r3
103+
; CHECK-PWR9-NEXT: std r0, 192(r1)
104104
; CHECK-PWR9-NEXT: bl callee
105105
; CHECK-PWR9-NEXT: nop
106106
; CHECK-PWR9-NEXT: addi r1, r1, 176
@@ -119,8 +119,8 @@ define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unna
119119
; CHECK-PWR8-LABEL: caller3:
120120
; CHECK-PWR8: # %bb.0: # %entry
121121
; CHECK-PWR8-NEXT: mflr r0
122-
; CHECK-PWR8-NEXT: std r0, 16(r1)
123122
; CHECK-PWR8-NEXT: stdu r1, -240(r1)
123+
; CHECK-PWR8-NEXT: std r0, 256(r1)
124124
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240
125125
; CHECK-PWR8-NEXT: .cfi_offset lr, 16
126126
; CHECK-PWR8-NEXT: .cfi_offset v20, -192
@@ -147,8 +147,8 @@ define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unna
147147
; CHECK-PWR9-LABEL: caller3:
148148
; CHECK-PWR9: # %bb.0: # %entry
149149
; CHECK-PWR9-NEXT: mflr r0
150-
; CHECK-PWR9-NEXT: std r0, 16(r1)
151150
; CHECK-PWR9-NEXT: stdu r1, -224(r1)
151+
; CHECK-PWR9-NEXT: std r0, 240(r1)
152152
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
153153
; CHECK-PWR9-NEXT: .cfi_offset lr, 16
154154
; CHECK-PWR9-NEXT: .cfi_offset v20, -192
@@ -177,8 +177,8 @@ define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unna
177177
; CHECK-PWR8-LABEL: caller4:
178178
; CHECK-PWR8: # %bb.0: # %entry
179179
; CHECK-PWR8-NEXT: mflr r0
180-
; CHECK-PWR8-NEXT: std r0, 16(r1)
181180
; CHECK-PWR8-NEXT: stdu r1, -240(r1)
181+
; CHECK-PWR8-NEXT: std r0, 256(r1)
182182
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240
183183
; CHECK-PWR8-NEXT: .cfi_offset lr, 16
184184
; CHECK-PWR8-NEXT: .cfi_offset v20, -192
@@ -205,8 +205,8 @@ define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unna
205205
; CHECK-PWR9-LABEL: caller4:
206206
; CHECK-PWR9: # %bb.0: # %entry
207207
; CHECK-PWR9-NEXT: mflr r0
208-
; CHECK-PWR9-NEXT: std r0, 16(r1)
209208
; CHECK-PWR9-NEXT: stdu r1, -224(r1)
209+
; CHECK-PWR9-NEXT: std r0, 240(r1)
210210
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
211211
; CHECK-PWR9-NEXT: .cfi_offset lr, 16
212212
; CHECK-PWR9-NEXT: .cfi_offset v20, -192
@@ -235,8 +235,8 @@ define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local
235235
; CHECK-PWR8-LABEL: caller_mixed:
236236
; CHECK-PWR8: # %bb.0: # %entry
237237
; CHECK-PWR8-NEXT: mflr r0
238-
; CHECK-PWR8-NEXT: std r0, 16(r1)
239238
; CHECK-PWR8-NEXT: stdu r1, -528(r1)
239+
; CHECK-PWR8-NEXT: std r0, 544(r1)
240240
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 528
241241
; CHECK-PWR8-NEXT: .cfi_offset lr, 16
242242
; CHECK-PWR8-NEXT: .cfi_offset r14, -288
@@ -269,8 +269,8 @@ define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local
269269
; CHECK-PWR9-LABEL: caller_mixed:
270270
; CHECK-PWR9: # %bb.0: # %entry
271271
; CHECK-PWR9-NEXT: mflr r0
272-
; CHECK-PWR9-NEXT: std r0, 16(r1)
273272
; CHECK-PWR9-NEXT: stdu r1, -512(r1)
273+
; CHECK-PWR9-NEXT: std r0, 528(r1)
274274
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 512
275275
; CHECK-PWR9-NEXT: .cfi_offset lr, 16
276276
; CHECK-PWR9-NEXT: .cfi_offset r14, -288

‎llvm/test/CodeGen/PowerPC/Frames-dyn-alloca-with-func-call.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -49,9 +49,9 @@ declare i32 @bar(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr)
4949

5050
; PPC32-LINUX-LABEL: foo
5151
; PPC32-LINUX: mflr 0
52-
; PPC32-LINUX: stw 0, 4(1)
5352
; PPC32-LINUX: stwu 1, -32(1)
5453
; PPC32-LINUX: stw 31, 28(1)
54+
; PPC32-LINUX: stw 0, 36(1)
5555
; PPC32-LINUX: mr 31, 1
5656
; PPC32-LINUX: addi 3, 31, 32
5757
; PPC32-LINUX: stwux 3, 1, 10
@@ -85,13 +85,13 @@ declare i32 @bar(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr)
8585
; PPC32-LINUX: blr
8686

8787
; PPC64-LABEL: foo
88-
; PPC64: mflr 0
89-
; PPC64: std 31, -8(1)
90-
; PPC64: std 0, 16(1)
91-
; PPC64: stdu 1, -160(1)
92-
; PPC64: mr 31, 1
93-
; PPC64: addi 3, 31, 160
94-
; PPC64: stdux 3, 1, 10
88+
; PPC64: mflr 0
89+
; PPC64: std 31, -8(1)
90+
; PPC64: stdu 1, -160(1)
91+
; PPC64-DAG: mr 31, 1
92+
; PPC64-DAG: std 0, 176(1)
93+
; PPC64: addi 3, 31, 160
94+
; PPC64: stdux 3, 1, 10
9595

9696
; Allocated area is referred by stack pointer.
9797
; PPC64: addi 11, 1, 128
@@ -122,9 +122,9 @@ declare i32 @bar(ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr)
122122

123123
; PPC32-AIX: mflr 0
124124
; PPC32-AIX: stw 31, -4(1)
125-
; PPC32-AIX: stw 0, 8(1)
126125
; PPC32-AIX: stwu 1, -80(1)
127126
; PPC32-AIX: mr 31, 1
127+
; PPC32-AIX: stw 0, 88(1)
128128
; PPC32-AIX: addi 3, 31, 80
129129
; PPC32-AIX: stwux 3, 1, 10
130130

‎llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,9 +18,9 @@ define noalias ptr @_ZN2CC3funEv(ptr %this) nounwind {
1818
; CHECK: # %bb.0: # %entry
1919
; CHECK-NEXT: mflr 0
2020
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
21-
; CHECK-NEXT: std 0, 16(1)
2221
; CHECK-NEXT: stdu 1, -48(1)
2322
; CHECK-NEXT: std 2, 24(1)
23+
; CHECK-NEXT: std 0, 64(1)
2424
; CHECK-NEXT: mr 30, 3
2525
; CHECK-NEXT: ld 12, 0(3)
2626
; CHECK-NEXT: mtctr 12

‎llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,10 +157,10 @@ define dso_local void @test_Array() nounwind {
157157
; CHECK-LE-LABEL: test_Array:
158158
; CHECK-LE: # %bb.0: # %entry
159159
; CHECK-LE-NEXT: mflr r0
160-
; CHECK-LE-NEXT: std r0, 16(r1)
161160
; CHECK-LE-NEXT: stdu r1, -176(r1)
162161
; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
163162
; CHECK-LE-NEXT: li r3, 0
163+
; CHECK-LE-NEXT: std r0, 192(r1)
164164
; CHECK-LE-NEXT: li r6, 65
165165
; CHECK-LE-NEXT: addi r5, r1, 46
166166
; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
@@ -190,11 +190,11 @@ define dso_local void @test_Array() nounwind {
190190
; CHECK-BE-LABEL: test_Array:
191191
; CHECK-BE: # %bb.0: # %entry
192192
; CHECK-BE-NEXT: mflr r0
193-
; CHECK-BE-NEXT: std r0, 16(r1)
194193
; CHECK-BE-NEXT: stdu r1, -256(r1)
195194
; CHECK-BE-NEXT: addis r5, r2, Arr1@toc@ha
196195
; CHECK-BE-NEXT: li r3, 0
197196
; CHECK-BE-NEXT: addi r5, r5, Arr1@toc@l
197+
; CHECK-BE-NEXT: std r0, 272(r1)
198198
; CHECK-BE-NEXT: addi r4, r1, 126
199199
; CHECK-BE-NEXT: li r6, 65
200200
; CHECK-BE-NEXT: stw r3, 124(r1)

‎llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@ define signext i32 @main() nounwind {
1212
; CHECK-LABEL: main:
1313
; CHECK: # %bb.0: # %L.entry
1414
; CHECK-NEXT: mflr 0
15-
; CHECK-NEXT: std 0, 16(1)
1615
; CHECK-NEXT: stdu 1, -48(1)
1716
; CHECK-NEXT: li 3, -32477
17+
; CHECK-NEXT: std 0, 64(1)
1818
; CHECK-NEXT: li 4, 234
1919
; CHECK-NEXT: addi 6, 1, 46
2020
; CHECK-NEXT: sth 3, 46(1)
@@ -65,16 +65,16 @@ define signext i32 @main() nounwind {
6565
; CHECK-P7-LABEL: main:
6666
; CHECK-P7: # %bb.0: # %L.entry
6767
; CHECK-P7-NEXT: mflr 0
68-
; CHECK-P7-NEXT: std 0, 16(1)
6968
; CHECK-P7-NEXT: stdu 1, -48(1)
7069
; CHECK-P7-NEXT: li 3, -32477
7170
; CHECK-P7-NEXT: lis 5, 0
7271
; CHECK-P7-NEXT: addi 4, 1, 46
7372
; CHECK-P7-NEXT: li 7, 0
73+
; CHECK-P7-NEXT: std 0, 64(1)
7474
; CHECK-P7-NEXT: sth 3, 46(1)
7575
; CHECK-P7-NEXT: li 6, 234
76-
; CHECK-P7-NEXT: ori 5, 5, 33059
7776
; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27
77+
; CHECK-P7-NEXT: ori 5, 5, 33059
7878
; CHECK-P7-NEXT: ori 7, 7, 65535
7979
; CHECK-P7-NEXT: sync
8080
; CHECK-P7-NEXT: slw 6, 6, 3

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