Skip to content

Commit edcdc81

Browse files
floatshadownikic
authored andcommitted
[ValueTracking] add UGT/UGE and SGT/SGE in isImpliedCondOperands
Partially `fix` llvm#62441. Extend isImpliedCondOperands() to handle ugt/uge and sgt/sge predicates. alive2 proof: https://alive2.llvm.org/ce/z/jLFDAv and https://alive2.llvm.org/ce/z/Z8idUd Differential Revision: https://reviews.llvm.org/D149510
1 parent 2444fb9 commit edcdc81

File tree

2 files changed

+18
-20
lines changed

2 files changed

+18
-20
lines changed

llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8144,12 +8144,26 @@ isImpliedCondOperands(CmpInst::Predicate Pred, const Value *ALHS,
81448144
return true;
81458145
return std::nullopt;
81468146

8147+
case CmpInst::ICMP_SGT:
8148+
case CmpInst::ICMP_SGE:
8149+
if (isTruePredicate(CmpInst::ICMP_SLE, ALHS, BLHS, DL, Depth) &&
8150+
isTruePredicate(CmpInst::ICMP_SLE, BRHS, ARHS, DL, Depth))
8151+
return true;
8152+
return std::nullopt;
8153+
81478154
case CmpInst::ICMP_ULT:
81488155
case CmpInst::ICMP_ULE:
81498156
if (isTruePredicate(CmpInst::ICMP_ULE, BLHS, ALHS, DL, Depth) &&
81508157
isTruePredicate(CmpInst::ICMP_ULE, ARHS, BRHS, DL, Depth))
81518158
return true;
81528159
return std::nullopt;
8160+
8161+
case CmpInst::ICMP_UGT:
8162+
case CmpInst::ICMP_UGE:
8163+
if (isTruePredicate(CmpInst::ICMP_ULE, ALHS, BLHS, DL, Depth) &&
8164+
isTruePredicate(CmpInst::ICMP_ULE, BRHS, ARHS, DL, Depth))
8165+
return true;
8166+
return std::nullopt;
81538167
}
81548168
}
81558169

llvm/test/Transforms/InstSimplify/implies.ll

Lines changed: 4 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -271,11 +271,7 @@ define i1 @test_sle(i32 %length.i, i32 %i) {
271271
; X +_{nsw} 1 <(s) Y ==> X <(s) Y
272272
define i1 @test_sgt_icmp(i32 %length.i, i32 %i) {
273273
; CHECK-LABEL: @test_sgt_icmp(
274-
; CHECK-NEXT: [[IPLUS1:%.*]] = add nsw i32 [[I:%.*]], 1
275-
; CHECK-NEXT: [[VAR29:%.*]] = icmp sgt i32 [[LENGTH_I:%.*]], [[I]]
276-
; CHECK-NEXT: [[VAR30:%.*]] = icmp sgt i32 [[LENGTH_I]], [[IPLUS1]]
277-
; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[VAR30]], [[VAR29]]
278-
; CHECK-NEXT: ret i1 [[RES]]
274+
; CHECK-NEXT: ret i1 true
279275
;
280276
%iplus1 = add nsw i32 %i, 1
281277
%var29 = icmp sgt i32 %length.i, %i
@@ -287,11 +283,7 @@ define i1 @test_sgt_icmp(i32 %length.i, i32 %i) {
287283
; X +_{nsw} 1 <=(s) Y ==> X <=(s) Y
288284
define i1 @test_sge_icmp(i32 %length.i, i32 %i) {
289285
; CHECK-LABEL: @test_sge_icmp(
290-
; CHECK-NEXT: [[IPLUS1:%.*]] = add nsw i32 [[I:%.*]], 1
291-
; CHECK-NEXT: [[VAR29:%.*]] = icmp sge i32 [[LENGTH_I:%.*]], [[I]]
292-
; CHECK-NEXT: [[VAR30:%.*]] = icmp sge i32 [[LENGTH_I]], [[IPLUS1]]
293-
; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[VAR30]], [[VAR29]]
294-
; CHECK-NEXT: ret i1 [[RES]]
286+
; CHECK-NEXT: ret i1 true
295287
;
296288
%iplus1 = add nsw i32 %i, 1
297289
%var29 = icmp sge i32 %length.i, %i
@@ -303,11 +295,7 @@ define i1 @test_sge_icmp(i32 %length.i, i32 %i) {
303295
; X +_{nuw} 1 <(u) Y ==> X <(u) Y
304296
define i1 @test_ugt_icmp(i32 %length.i, i32 %i) {
305297
; CHECK-LABEL: @test_ugt_icmp(
306-
; CHECK-NEXT: [[IPLUS1:%.*]] = add nuw i32 [[I:%.*]], 1
307-
; CHECK-NEXT: [[VAR29:%.*]] = icmp ugt i32 [[LENGTH_I:%.*]], [[I]]
308-
; CHECK-NEXT: [[VAR30:%.*]] = icmp ugt i32 [[LENGTH_I]], [[IPLUS1]]
309-
; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[VAR30]], [[VAR29]]
310-
; CHECK-NEXT: ret i1 [[RES]]
298+
; CHECK-NEXT: ret i1 true
311299
;
312300
%iplus1 = add nuw i32 %i, 1
313301
%var29 = icmp ugt i32 %length.i, %i
@@ -319,11 +307,7 @@ define i1 @test_ugt_icmp(i32 %length.i, i32 %i) {
319307
; X +_{nuw} 1 <=(u) Y ==> X <=(u) Y
320308
define i1 @test_uge_icmp(i32 %length.i, i32 %i) {
321309
; CHECK-LABEL: @test_uge_icmp(
322-
; CHECK-NEXT: [[IPLUS1:%.*]] = add nuw i32 [[I:%.*]], 1
323-
; CHECK-NEXT: [[VAR29:%.*]] = icmp uge i32 [[LENGTH_I:%.*]], [[I]]
324-
; CHECK-NEXT: [[VAR30:%.*]] = icmp uge i32 [[LENGTH_I]], [[IPLUS1]]
325-
; CHECK-NEXT: [[RES:%.*]] = icmp ule i1 [[VAR30]], [[VAR29]]
326-
; CHECK-NEXT: ret i1 [[RES]]
310+
; CHECK-NEXT: ret i1 true
327311
;
328312
%iplus1 = add nuw i32 %i, 1
329313
%var29 = icmp uge i32 %length.i, %i

0 commit comments

Comments
 (0)