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[RISCV] Fix offset computation for RVV
In D97111 we changed the RVV frame layout when using sp or bp to address the stack slots so we could address the emergency stack slot. The idea is to put the RVV objects as far as possible (in offset terms) from the frame reference register (sp / fp / bp). When using fp this happens naturally because the RVV objects are already the top of the stack and due to the constraints of RVV (VLENB being a power of two >= 128) the stack remains aligned. The rest of this summary does not apply to this case. When using sp / bp we need to skip the non-RVV stack slots. The size of the the non-RVV objects is computed subtracting the callee saved register size (whose computation is added in D97111 itself) to the total size of the stack (which does not account for RVV stack slots). However, when doing so we round to 16 bytes when computing that size and we end emitting a smaller offset that may belong to a scalar stack slot (see D98801). So this change removes that rounding. Also, because we want the RVV objects be between the non-RVV stack slots and the callee-saved register slots, we need to make sure the RVV objects are properly aligned to 8 bytes. Adding a padding of 8 would render the stack unaligned. So when allocating space for RVV (only when we don't use fp) we need to have extra padding that preserves the stack alignment. This way we can round to 8 bytes the offset that skips the non-RVV objects and we do not misalign the whole stack in the way. In some circumstances this means that the RVV objects may have padding before (=lower offsets from sp/bp) and after (before the CSR stack slots). Differential Revision: https://reviews.llvm.org/D98802
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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 81 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,7 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
323323
// 2. SP = SP - RVV stack size
324324
BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
325325
.addReg(SPReg)
326-
.addReg(FactorRegister);
326+
.addReg(FactorRegister, RegState::Kill);
327327
}
328328

329329
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
@@ -385,7 +385,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
385385

386386
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
387387
// investigation. Get the number of bytes to allocate from the FrameInfo.
388-
uint64_t StackSize = MFI.getStackSize();
388+
uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
389389
uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
390390
uint64_t RVVStackSize = RVFI->getRVVStackSize();
391391

@@ -560,7 +560,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
560560
if (!CSI.empty())
561561
LastFrameDestroy = std::prev(MBBI, CSI.size());
562562

563-
uint64_t StackSize = MFI.getStackSize();
563+
uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
564564
uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
565565
uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
566566
uint64_t RVVStackSize = RVFI->getRVVStackSize();
@@ -637,48 +637,72 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
637637
if (FirstSPAdjustAmount)
638638
Offset += StackOffset::getFixed(FirstSPAdjustAmount);
639639
else
640-
Offset += StackOffset::getFixed(MFI.getStackSize());
640+
Offset +=
641+
StackOffset::getFixed(MFI.getStackSize() + RVFI->getRVVPadding());
641642
} else if (RI->needsStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
642643
// If the stack was realigned, the frame pointer is set in order to allow
643644
// SP to be restored, so we need another base register to record the stack
644645
// after realignment.
645646
if (hasBP(MF)) {
646647
FrameReg = RISCVABI::getBPReg();
647648
// |--------------------------| -- <-- FP
648-
// | callee-saved registers | | <---------.
649-
// |--------------------------| -- |
650-
// | realignment (the size of | | |
651-
// | this area is not counted | | |
652-
// | in MFI.getStackSize()) | | |
653-
// |--------------------------| -- |-- MFI.getStackSize()
654-
// | RVV objects | | |
655-
// |--------------------------| -- |
656-
// | scalar local variables | | <---------'
649+
// | callee-saved registers | | <----.
650+
// |--------------------------| -- |
651+
// | realignment (the size of | | |
652+
// | this area is not counted | | |
653+
// | in MFI.getStackSize()) | | |
654+
// |--------------------------| -- |
655+
// | Padding after RVV | | |
656+
// | (not counted in | | |
657+
// | MFI.getStackSize() | | |
658+
// |--------------------------| -- |-- MFI.getStackSize()
659+
// | RVV objects | | |
660+
// | (not counted in | | |
661+
// | MFI.getStackSize() | | |
662+
// |--------------------------| -- |
663+
// | Padding before RVV | | |
664+
// | (not counted in | | |
665+
// | MFI.getStackSize() | | |
666+
// |--------------------------| -- |
667+
// | scalar local variables | | <----'
657668
// |--------------------------| -- <-- BP
658669
// | VarSize objects | |
659670
// |--------------------------| -- <-- SP
660671
} else {
661672
FrameReg = RISCV::X2;
662673
// |--------------------------| -- <-- FP
663-
// | callee-saved registers | | <---------.
664-
// |--------------------------| -- |
665-
// | realignment (the size of | | |
666-
// | this area is not counted | | |
667-
// | in MFI.getStackSize()) | | |
668-
// |--------------------------| -- |-- MFI.getStackSize()
669-
// | RVV objects | | |
670-
// |--------------------------| -- |
671-
// | scalar local variables | | <---------'
674+
// | callee-saved registers | | <----.
675+
// |--------------------------| -- |
676+
// | realignment (the size of | | |
677+
// | this area is not counted | | |
678+
// | in MFI.getStackSize()) | | |
679+
// |--------------------------| -- |
680+
// | Padding after RVV | | |
681+
// | (not counted in | | |
682+
// | MFI.getStackSize() | | |
683+
// |--------------------------| -- |-- MFI.getStackSize()
684+
// | RVV objects | | |
685+
// | (not counted in | | |
686+
// | MFI.getStackSize() | | |
687+
// |--------------------------| -- |
688+
// | Padding before RVV | | |
689+
// | (not counted in | | |
690+
// | MFI.getStackSize() | | |
691+
// |--------------------------| -- |
692+
// | scalar local variables | | <----'
672693
// |--------------------------| -- <-- SP
673694
}
695+
// The total amount of padding surrounding RVV objects is described by
696+
// RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
697+
// objects to 8 bytes.
674698
if (MFI.getStackID(FI) == TargetStackID::Default) {
675699
Offset += StackOffset::getFixed(MFI.getStackSize());
676700
if (FI < 0)
677701
Offset += StackOffset::getFixed(RVFI->getLibCallStackSize());
678702
} else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
679-
Offset +=
680-
StackOffset::get(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(),
681-
RVFI->getRVVStackSize());
703+
Offset += StackOffset::get(
704+
alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
705+
RVFI->getRVVStackSize());
682706
}
683707
} else {
684708
FrameReg = RI->getFrameRegister(MF);
@@ -704,20 +728,34 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
704728
// When using SP to access frame objects, we need to add RVV stack size.
705729
//
706730
// |--------------------------| -- <-- FP
707-
// | callee-saved registers | |<--------.
708-
// |--------------------------| -- |
709-
// | RVV objects | | |-- MFI.getStackSize()
710-
// |--------------------------| -- |
711-
// | scalar local variables | |<--------'
731+
// | callee-saved registers | | <----.
732+
// |--------------------------| -- |
733+
// | Padding after RVV | | |
734+
// | (not counted in | | |
735+
// | MFI.getStackSize() | | |
736+
// |--------------------------| -- |
737+
// | RVV objects | | |-- MFI.getStackSize()
738+
// | (not counted in | | |
739+
// | MFI.getStackSize() | | |
740+
// |--------------------------| -- |
741+
// | Padding before RVV | | |
742+
// | (not counted in | | |
743+
// | MFI.getStackSize() | | |
744+
// |--------------------------| -- |
745+
// | scalar local variables | | <----'
712746
// |--------------------------| -- <-- SP
747+
//
748+
// The total amount of padding surrounding RVV objects is described by
749+
// RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
750+
// objects to 8 bytes.
713751
if (MFI.getStackID(FI) == TargetStackID::Default) {
714752
Offset += StackOffset::getFixed(MFI.getStackSize());
715753
if (FI < 0)
716754
Offset += StackOffset::getFixed(RVFI->getLibCallStackSize());
717755
} else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
718-
Offset += StackOffset::get(MFI.getStackSize() -
719-
RVFI->getCalleeSavedStackSize(),
720-
RVFI->getRVVStackSize());
756+
Offset += StackOffset::get(
757+
alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
758+
RVFI->getRVVStackSize());
721759
}
722760
}
723761
}
@@ -822,32 +860,29 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
822860
RegInfo->getSpillAlign(*RC), false);
823861
RS->addScavengingFrameIndex(RegScavFI);
824862
}
825-
}
826863

827-
void RISCVFrameLowering::processFunctionBeforeFrameIndicesReplaced(
828-
MachineFunction &MF, RegScavenger *RS) const {
829-
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
830-
const MachineFrameInfo &MFI = MF.getFrameInfo();
831864
if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) {
832865
RVFI->setCalleeSavedStackSize(0);
833866
return;
834867
}
835868

836-
int64_t MinOffset = std::numeric_limits<int64_t>::max();
837-
int64_t MaxOffset = std::numeric_limits<int64_t>::min();
869+
unsigned Size = 0;
838870
for (const auto &Info : MFI.getCalleeSavedInfo()) {
839871
int FrameIdx = Info.getFrameIdx();
840872
if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
841873
continue;
842874

843-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
844-
int64_t ObjSize = MFI.getObjectSize(FrameIdx);
845-
MinOffset = std::min<int64_t>(Offset, MinOffset);
846-
MaxOffset = std::max<int64_t>(Offset + ObjSize, MaxOffset);
875+
Size += MFI.getObjectSize(FrameIdx);
847876
}
848-
849-
unsigned Size = alignTo(MaxOffset - MinOffset, 16);
850877
RVFI->setCalleeSavedStackSize(Size);
878+
879+
// Padding required to keep the RVV stack aligned to 8 bytes
880+
// within the main stack. We only need this when not using FP.
881+
if (RVVStackSize && !hasFP(MF) && Size % 8 != 0) {
882+
// Because we add the padding to the size of the stack, adding
883+
// getStackAlign() will keep it aligned.
884+
RVFI->setRVVPadding(getStackAlign().value());
885+
}
851886
}
852887

853888
// Not preserve stack space within prologue for outgoing variables when the

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,6 @@ class RISCVFrameLowering : public TargetFrameLowering {
6868
bool isSupportedStackID(TargetStackID::Value ID) const override;
6969
TargetStackID::Value getStackIDForScalableVectors() const override;
7070

71-
void processFunctionBeforeFrameIndicesReplaced(
72-
MachineFunction &MF, RegScavenger *RS = nullptr) const override;
73-
7471
protected:
7572
const RISCVSubtarget &STI;
7673

‎llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
3434
unsigned LibCallStackSize = 0;
3535
/// Size of RVV stack.
3636
uint64_t RVVStackSize = 0;
37+
/// Padding required to keep RVV stack aligned within the main stack.
38+
uint64_t RVVPadding = 0;
3739
/// Size of stack frame to save callee saved registers
3840
unsigned CalleeSavedStackSize = 0;
3941

@@ -66,6 +68,9 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
6668
uint64_t getRVVStackSize() const { return RVVStackSize; }
6769
void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
6870

71+
uint64_t getRVVPadding() const { return RVVPadding; }
72+
void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
73+
6974
unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
7075
void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
7176
};

‎llvm/test/CodeGen/RISCV/rvv/localvar.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -256,15 +256,15 @@ define void @local_var_m2_with_bp(i64 %n) {
256256
; RV64IV-NEXT: csrr a2, vlenb
257257
; RV64IV-NEXT: slli a2, a2, 1
258258
; RV64IV-NEXT: add a2, s1, a2
259-
; RV64IV-NEXT: addi a2, a2, 224
259+
; RV64IV-NEXT: addi a2, a2, 232
260260
; RV64IV-NEXT: call notdead2@plt
261261
; RV64IV-NEXT: lw a0, 124(s1)
262262
; RV64IV-NEXT: csrr a0, vlenb
263263
; RV64IV-NEXT: slli a0, a0, 1
264264
; RV64IV-NEXT: add a0, s1, a0
265-
; RV64IV-NEXT: addi a0, a0, 224
265+
; RV64IV-NEXT: addi a0, a0, 232
266266
; RV64IV-NEXT: vl2r.v v26, (a0)
267-
; RV64IV-NEXT: addi a0, s1, 224
267+
; RV64IV-NEXT: addi a0, s1, 232
268268
; RV64IV-NEXT: vl2r.v v26, (a0)
269269
; RV64IV-NEXT: lw a0, 120(s1)
270270
; RV64IV-NEXT: addi sp, s0, -256

‎llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -9,59 +9,67 @@
99
define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 %gvl) nounwind
1010
; SPILL-O0-LABEL: foo:
1111
; SPILL-O0: # %bb.0:
12-
; SPILL-O0-NEXT: addi sp, sp, -16
13-
; SPILL-O0-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
12+
; SPILL-O0-NEXT: addi sp, sp, -32
13+
; SPILL-O0-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
1414
; SPILL-O0-NEXT: csrr a1, vlenb
1515
; SPILL-O0-NEXT: slli a1, a1, 1
1616
; SPILL-O0-NEXT: sub sp, sp, a1
1717
; SPILL-O0-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
1818
; SPILL-O0-NEXT: csrr a1, vlenb
1919
; SPILL-O0-NEXT: add a1, sp, a1
20+
; SPILL-O0-NEXT: addi a1, a1, 16
2021
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
2122
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
2223
; SPILL-O0-NEXT: vfadd.vv v25, v8, v9
23-
; SPILL-O0-NEXT: vs1r.v v25, (sp) # Unknown-size Folded Spill
24+
; SPILL-O0-NEXT: addi a0, sp, 16
25+
; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
2426
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
2527
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
2628
; SPILL-O0-NEXT: call puts@plt
27-
; SPILL-O0-NEXT: vl1r.v v25, (sp) # Unknown-size Folded Reload
29+
; SPILL-O0-NEXT: addi a1, sp, 16
30+
; SPILL-O0-NEXT: vl1r.v v25, (a1) # Unknown-size Folded Reload
2831
; SPILL-O0-NEXT: csrr a1, vlenb
2932
; SPILL-O0-NEXT: add a1, sp, a1
33+
; SPILL-O0-NEXT: addi a1, a1, 16
3034
; SPILL-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload
3135
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
32-
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
36+
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
3337
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
3438
; SPILL-O0-NEXT: vfadd.vv v8, v8, v25
3539
; SPILL-O0-NEXT: csrr a0, vlenb
3640
; SPILL-O0-NEXT: slli a0, a0, 1
3741
; SPILL-O0-NEXT: add sp, sp, a0
38-
; SPILL-O0-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
39-
; SPILL-O0-NEXT: addi sp, sp, 16
42+
; SPILL-O0-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
43+
; SPILL-O0-NEXT: addi sp, sp, 32
4044
; SPILL-O0-NEXT: ret
4145
;
4246
; SPILL-O2-LABEL: foo:
4347
; SPILL-O2: # %bb.0:
4448
; SPILL-O2-NEXT: addi sp, sp, -16
4549
; SPILL-O2-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
46-
; SPILL-O2-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
50+
; SPILL-O2-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
4751
; SPILL-O2-NEXT: csrr a1, vlenb
4852
; SPILL-O2-NEXT: slli a1, a1, 1
4953
; SPILL-O2-NEXT: sub sp, sp, a1
5054
; SPILL-O2-NEXT: mv s0, a0
51-
; SPILL-O2-NEXT: vs1r.v v8, (sp) # Unknown-size Folded Spill
55+
; SPILL-O2-NEXT: addi a1, sp, 8
56+
; SPILL-O2-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
5257
; SPILL-O2-NEXT: vsetvli a0, a0, e64,m1,ta,mu
5358
; SPILL-O2-NEXT: vfadd.vv v25, v8, v9
5459
; SPILL-O2-NEXT: csrr a0, vlenb
5560
; SPILL-O2-NEXT: add a0, sp, a0
61+
; SPILL-O2-NEXT: addi a0, a0, 8
5662
; SPILL-O2-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
5763
; SPILL-O2-NEXT: lui a0, %hi(.L.str)
5864
; SPILL-O2-NEXT: addi a0, a0, %lo(.L.str)
5965
; SPILL-O2-NEXT: call puts@plt
6066
; SPILL-O2-NEXT: vsetvli a0, s0, e64,m1,ta,mu
6167
; SPILL-O2-NEXT: csrr a0, vlenb
6268
; SPILL-O2-NEXT: add a0, sp, a0
69+
; SPILL-O2-NEXT: addi a0, a0, 8
6370
; SPILL-O2-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
64-
; SPILL-O2-NEXT: vl1r.v v26, (sp) # Unknown-size Folded Reload
71+
; SPILL-O2-NEXT: addi a0, sp, 8
72+
; SPILL-O2-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
6573
; SPILL-O2-NEXT: vfadd.vv v8, v26, v25
6674
; SPILL-O2-NEXT: csrr a0, vlenb
6775
; SPILL-O2-NEXT: slli a0, a0, 1
@@ -78,4 +86,4 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
7886
}
7987

8088
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 %gvl)
81-
declare i32 @puts(i8*);
89+
declare i32 @puts(i8*);

‎llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,22 +17,22 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
1717
; SPILL-O0-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
1818
; SPILL-O0-NEXT: csrr a1, vlenb
1919
; SPILL-O0-NEXT: add a1, sp, a1
20-
; SPILL-O0-NEXT: addi a1, a1, 16
20+
; SPILL-O0-NEXT: addi a1, a1, 24
2121
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
2222
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
2323
; SPILL-O0-NEXT: vfadd.vv v25, v8, v9
24-
; SPILL-O0-NEXT: addi a0, sp, 16
24+
; SPILL-O0-NEXT: addi a0, sp, 24
2525
; SPILL-O0-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
2626
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
2727
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
2828
; SPILL-O0-NEXT: call puts@plt
29-
; SPILL-O0-NEXT: addi a1, sp, 16
29+
; SPILL-O0-NEXT: addi a1, sp, 24
3030
; SPILL-O0-NEXT: vl1r.v v25, (a1) # Unknown-size Folded Reload
3131
; SPILL-O0-NEXT: csrr a1, vlenb
3232
; SPILL-O0-NEXT: add a1, sp, a1
33-
; SPILL-O0-NEXT: addi a1, a1, 16
33+
; SPILL-O0-NEXT: addi a1, a1, 24
3434
; SPILL-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload
35-
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
35+
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
3636
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
3737
; SPILL-O0-NEXT: vsetvli a0, a0, e64,m1,ta,mu
3838
; SPILL-O0-NEXT: vfadd.vv v8, v8, v25

‎llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -107,9 +107,9 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
107107
; CHECK-NEXT: csrr a2, vlenb
108108
; CHECK-NEXT: slli a2, a2, 1
109109
; CHECK-NEXT: add a2, s1, a2
110-
; CHECK-NEXT: addi a2, a2, 96
110+
; CHECK-NEXT: addi a2, a2, 104
111111
; CHECK-NEXT: vl1re64.v v25, (a2)
112-
; CHECK-NEXT: addi a2, s1, 96
112+
; CHECK-NEXT: addi a2, s1, 104
113113
; CHECK-NEXT: vl2re64.v v26, (a2)
114114
; CHECK-NEXT: lw a2, 64(s1)
115115
; CHECK-NEXT: slli a1, a1, 2

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