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Merge pull request #7994 from fhahn/cgp-free-exts
[CGP] Avoid replacing a free ext with multiple other exts.
2 parents 6e3538d + e5bcb48 commit efd5925

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4 files changed

+188
-33
lines changed

4 files changed

+188
-33
lines changed

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5955,15 +5955,18 @@ bool CodeGenPrepare::tryToPromoteExts(
59555955
// cut this search path, because it means we degrade the code quality.
59565956
// With exactly 2, the transformation is neutral, because we will merge
59575957
// one extension but leave one. However, we optimistically keep going,
5958-
// because the new extension may be removed too.
5958+
// because the new extension may be removed too. Also avoid replacing a
5959+
// single free extension with multiple extensions, as this increases the
5960+
// number of IR instructions while not providing any savings.
59595961
long long TotalCreatedInstsCost = CreatedInstsCost + NewCreatedInstsCost;
59605962
// FIXME: It would be possible to propagate a negative value instead of
59615963
// conservatively ceiling it to 0.
59625964
TotalCreatedInstsCost =
59635965
std::max((long long)0, (TotalCreatedInstsCost - ExtCost));
59645966
if (!StressExtLdPromotion &&
59655967
(TotalCreatedInstsCost > 1 ||
5966-
!isPromotedInstructionLegal(*TLI, *DL, PromotedVal))) {
5968+
!isPromotedInstructionLegal(*TLI, *DL, PromotedVal) ||
5969+
(ExtCost == 0 && NewExts.size() > 1))) {
59675970
// This promotion is not profitable, rollback to the previous state, and
59685971
// save the current extension in ProfitablyMovedExts as the latest
59695972
// speculative promotion turned out to be unprofitable.

‎llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -525,10 +525,14 @@ entry:
525525
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
526526
;
527527
; This transformation should really happen only for stress mode.
528-
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
529-
; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
530-
; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
531-
; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
528+
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
529+
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
530+
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
531+
; STRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32
532+
;
533+
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
534+
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
535+
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
532536
;
533537
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
534538
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
@@ -580,9 +584,13 @@ entry:
580584
; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, ptr %p
581585
;
582586
; This transformation should really happen only for stress mode.
583-
; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
584-
; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
585-
; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
587+
; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64
588+
; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64
589+
; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]]
590+
;
591+
; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
592+
; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b
593+
; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64
586594
;
587595
; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
588596
; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b

‎llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc -mtriple=arm64-apple-macosx -o - %s | FileCheck %s
3+
4+
%struct.zot = type { ptr, i32, ptr, ptr, i32, i32, i32, i32, i32, i32 }
5+
6+
; FIXME: currently the AND is performed on 64 bit unnecessarily.
7+
8+
; Test cases where an AND is extended from i32 -> i64 which is free. Make
9+
; sure the extends do not get moved to the arguments, which would perform the
10+
; AND on 64 bits unnecessarily.
11+
12+
define void @avoid_promotion_1_and(ptr nocapture noundef %arg, ptr %p) {
13+
; CHECK-LABEL: avoid_promotion_1_and:
14+
; CHECK: ; %bb.0: ; %bb
15+
; CHECK-NEXT: mov w8, #10 ; =0xa
16+
; CHECK-NEXT: ldr w9, [x0, #52]
17+
; CHECK-NEXT: LBB0_1: ; %bb8
18+
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
19+
; CHECK-NEXT: cmp w9, #3
20+
; CHECK-NEXT: b.lo LBB0_1
21+
; CHECK-NEXT: ; %bb.2: ; %bb9
22+
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
23+
; CHECK-NEXT: ldr w10, [x0, #32]
24+
; CHECK-NEXT: ldr w11, [x1, #76]
25+
; CHECK-NEXT: ldr w12, [x1]
26+
; CHECK-NEXT: eor w10, w10, w11
27+
; CHECK-NEXT: and w10, w10, w12
28+
; CHECK-NEXT: str w10, [x0, #32]
29+
; CHECK-NEXT: strh w8, [x1, w10, uxtw #1]
30+
; CHECK-NEXT: b LBB0_1
31+
bb:
32+
%gep = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 9
33+
%l = load i32, ptr %gep, align 4
34+
%icmp = icmp ugt i32 %l, 2
35+
%gep1 = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 4
36+
%gep2 = getelementptr inbounds %struct.zot, ptr %arg, i64 0, i32 7
37+
br label %bb8
38+
39+
bb8: ; preds = %bb27, %bb
40+
br i1 %icmp, label %bb9, label %bb27
41+
42+
bb9: ; preds = %bb8
43+
%l10 = load i32, ptr %gep1, align 8
44+
%gep14 = getelementptr inbounds i32, ptr %p, i64 19
45+
%l15 = load i32, ptr %gep14, align 1
46+
%xor = xor i32 %l10, %l15
47+
%l17 = load i32, ptr %p, align 8
48+
%and = and i32 %xor, %l17
49+
store i32 %and, ptr %gep1, align 8
50+
%zext19 = zext i32 %and to i64
51+
%gep20 = getelementptr inbounds i16, ptr %p, i64 %zext19
52+
store i16 10, ptr %gep20, align 2
53+
br label %bb27
54+
55+
bb27: ; preds = %bb9, %bb8
56+
br label %bb8
57+
}
58+
59+
define void @avoid_promotion_2_and(ptr nocapture noundef %arg) {
60+
; CHECK-LABEL: avoid_promotion_2_and:
61+
; CHECK: ; %bb.0: ; %entry
62+
; CHECK-NEXT: add x8, x0, #32
63+
; CHECK-NEXT: b LBB1_2
64+
; CHECK-NEXT: LBB1_1: ; %latch
65+
; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
66+
; CHECK-NEXT: add x8, x8, #56
67+
; CHECK-NEXT: cmp w9, #2
68+
; CHECK-NEXT: b.ls LBB1_4
69+
; CHECK-NEXT: LBB1_2: ; %loop
70+
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
71+
; CHECK-NEXT: ldr w9, [x8, #20]
72+
; CHECK-NEXT: cmp w9, #3
73+
; CHECK-NEXT: b.lo LBB1_1
74+
; CHECK-NEXT: ; %bb.3: ; %then
75+
; CHECK-NEXT: ; in Loop: Header=BB1_2 Depth=1
76+
; CHECK-NEXT: ldp w13, w10, [x8, #12]
77+
; CHECK-NEXT: ldr x11, [x0]
78+
; CHECK-NEXT: ldr w12, [x8]
79+
; CHECK-NEXT: ldr w14, [x8, #8]
80+
; CHECK-NEXT: ldrb w11, [x11, x10]
81+
; CHECK-NEXT: lsl w12, w12, w13
82+
; CHECK-NEXT: eor w11, w12, w11
83+
; CHECK-NEXT: ldur w12, [x8, #-24]
84+
; CHECK-NEXT: and w11, w11, w14
85+
; CHECK-NEXT: ldp x15, x14, [x8, #-16]
86+
; CHECK-NEXT: ubfiz x13, x11, #1, #32
87+
; CHECK-NEXT: str w11, [x8]
88+
; CHECK-NEXT: and w11, w12, w10
89+
; CHECK-NEXT: ldrh w12, [x14, x13]
90+
; CHECK-NEXT: strh w12, [x15, w11, uxtw #1]
91+
; CHECK-NEXT: strh w10, [x14, x13]
92+
; CHECK-NEXT: b LBB1_1
93+
; CHECK-NEXT: LBB1_4: ; %exit
94+
; CHECK-NEXT: ret
95+
entry:
96+
br label %loop
97+
98+
loop:
99+
%p = phi i64 [ 0, %entry ], [ %p.next, %latch ]
100+
%gep = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 9
101+
%l = load i32, ptr %gep, align 4
102+
%icmp = icmp ugt i32 %l, 2
103+
%gep1 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 4
104+
%gep2 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 7
105+
%gep3 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 8
106+
%gep4 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 6
107+
%gep5 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 3
108+
%gep6 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 2
109+
%gep7 = getelementptr inbounds %struct.zot, ptr %arg, i64 %p, i32 1
110+
br i1 %icmp, label %then, label %latch
111+
112+
then:
113+
%l10 = load i32, ptr %gep1, align 8
114+
%l11 = load i32, ptr %gep2, align 4
115+
%shl = shl i32 %l10, %l11
116+
%l12 = load ptr, ptr %arg, align 8
117+
%l13 = load i32, ptr %gep3, align 8
118+
%zext = zext i32 %l13 to i64
119+
%gep14 = getelementptr inbounds i8, ptr %l12, i64 %zext
120+
%l15 = load i8, ptr %gep14, align 1
121+
%zext16 = zext i8 %l15 to i32
122+
%xor = xor i32 %shl, %zext16
123+
%l17 = load i32, ptr %gep4, align 8
124+
%and = and i32 %xor, %l17
125+
store i32 %and, ptr %gep1, align 8
126+
%l18 = load ptr, ptr %gep5, align 8
127+
%zext19 = zext i32 %and to i64
128+
%gep20 = getelementptr inbounds i16, ptr %l18, i64 %zext19
129+
%l21 = load i16, ptr %gep20, align 2
130+
%l22 = load ptr, ptr %gep6, align 8
131+
%l23 = load i32, ptr %gep7, align 8
132+
%and24 = and i32 %l23, %l13
133+
%zext25 = zext i32 %and24 to i64
134+
%gep26 = getelementptr inbounds i16, ptr %l22, i64 %zext25
135+
store i16 %l21, ptr %gep26, align 2
136+
%trunc = trunc i32 %l13 to i16
137+
store i16 %trunc, ptr %gep20, align 2
138+
br label %latch
139+
140+
latch:
141+
%p.next = add i64 %p, 1
142+
br i1 %icmp, label %loop, label %exit
143+
144+
exit:
145+
ret void
146+
}

‎llvm/test/CodeGen/AArch64/bfis-in-loop.ll

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -21,18 +21,17 @@ define i64 @bfis_in_loop_zero() {
2121
; CHECK-NEXT: .LBB0_1: // %midblock
2222
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
2323
; CHECK-NEXT: ldrh w10, [x9, #72]
24-
; CHECK-NEXT: cmp w10, #0
25-
; CHECK-NEXT: ubfx x11, x10, #8, #24
26-
; CHECK-NEXT: cset w12, ne
27-
; CHECK-NEXT: csel w8, w8, w11, eq
28-
; CHECK-NEXT: ldr x11, [x9, #8]
29-
; CHECK-NEXT: and x9, x10, #0xff
30-
; CHECK-NEXT: and x10, x0, #0xffffffff00000000
31-
; CHECK-NEXT: orr x9, x9, x8, lsl #8
32-
; CHECK-NEXT: orr x10, x10, x12, lsl #16
33-
; CHECK-NEXT: orr x0, x10, x9
34-
; CHECK-NEXT: ldr x9, [x11, #16]
35-
; CHECK-NEXT: cbnz x11, .LBB0_1
24+
; CHECK-NEXT: ldr x12, [x9, #8]
25+
; CHECK-NEXT: and x9, x0, #0xffffffff00000000
26+
; CHECK-NEXT: cmp w10, #0
27+
; CHECK-NEXT: lsr w11, w10, #8
28+
; CHECK-NEXT: csel w8, w8, w11, eq
29+
; CHECK-NEXT: cset w11, ne
30+
; CHECK-NEXT: orr x9, x9, x11, lsl #16
31+
; CHECK-NEXT: bfi w10, w8, #8, #24
32+
; CHECK-NEXT: orr x0, x9, x10
33+
; CHECK-NEXT: ldr x9, [x12, #16]
34+
; CHECK-NEXT: cbnz x12, .LBB0_1
3635
; CHECK-NEXT: // %bb.2: // %exit
3736
; CHECK-NEXT: ret
3837
entry:
@@ -89,18 +88,17 @@ define i64 @bfis_in_loop_undef() {
8988
; CHECK-NEXT: .LBB1_1: // %midblock
9089
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
9190
; CHECK-NEXT: ldrh w10, [x9, #72]
92-
; CHECK-NEXT: cmp w10, #0
93-
; CHECK-NEXT: ubfx x11, x10, #8, #24
94-
; CHECK-NEXT: cset w12, ne
95-
; CHECK-NEXT: csel w8, w8, w11, eq
96-
; CHECK-NEXT: ldr x11, [x9, #8]
97-
; CHECK-NEXT: and x9, x10, #0xff
98-
; CHECK-NEXT: and x10, x0, #0xffffffff00000000
99-
; CHECK-NEXT: orr x9, x9, x8, lsl #8
100-
; CHECK-NEXT: orr x10, x10, x12, lsl #16
101-
; CHECK-NEXT: orr x0, x10, x9
102-
; CHECK-NEXT: ldr x9, [x11, #16]
103-
; CHECK-NEXT: cbnz x11, .LBB1_1
91+
; CHECK-NEXT: ldr x12, [x9, #8]
92+
; CHECK-NEXT: and x9, x0, #0xffffffff00000000
93+
; CHECK-NEXT: cmp w10, #0
94+
; CHECK-NEXT: lsr w11, w10, #8
95+
; CHECK-NEXT: csel w8, w8, w11, eq
96+
; CHECK-NEXT: cset w11, ne
97+
; CHECK-NEXT: orr x9, x9, x11, lsl #16
98+
; CHECK-NEXT: bfi w10, w8, #8, #24
99+
; CHECK-NEXT: orr x0, x9, x10
100+
; CHECK-NEXT: ldr x9, [x12, #16]
101+
; CHECK-NEXT: cbnz x12, .LBB1_1
104102
; CHECK-NEXT: // %bb.2: // %exit
105103
; CHECK-NEXT: ret
106104
entry:

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