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davemgreendavemgreen
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[MachineScheduler] Enable AA in PostRA Machine scheduler
This adds AA to Post-RA Machine Scheduling, allowing the pass more freedom when handling memory operations. My understanding is that this was just never done, not that it is inherently incorrect to do so. The older PostRA List scheduler already makes use of AA, it's just that the MI PostRA Scheduler was never taught to use it. Differential Revision: https://reviews.llvm.org/D69814
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7 files changed

+51
-49
lines changed

7 files changed

+51
-49
lines changed

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -238,6 +238,7 @@ void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
238238
AU.setPreservesCFG();
239239
AU.addRequired<MachineDominatorTree>();
240240
AU.addRequired<MachineLoopInfo>();
241+
AU.addRequired<AAResultsWrapperPass>();
241242
AU.addRequired<TargetPassConfig>();
242243
MachineFunctionPass::getAnalysisUsage(AU);
243244
}
@@ -412,6 +413,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
412413
MF = &mf;
413414
MLI = &getAnalysis<MachineLoopInfo>();
414415
PassConfig = &getAnalysis<TargetPassConfig>();
416+
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
415417

416418
if (VerifyScheduling)
417419
MF->verify(this, "Before post machine scheduling.");

‎llvm/test/CodeGen/AArch64/merge-store-dependency.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,15 +17,15 @@ define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg
1717
; A53-NEXT: movi v0.2d, #0000000000000000
1818
; A53-NEXT: mov x8, x0
1919
; A53-NEXT: mov x19, x8
20-
; A53-NEXT: mov w9, #256
2120
; A53-NEXT: mov w0, w1
22-
; A53-NEXT: str q0, [x8]
21+
; A53-NEXT: mov w9, #256
2322
; A53-NEXT: str q0, [x19, #16]!
24-
; A53-NEXT: strh w9, [x8, #24]
2523
; A53-NEXT: str w1, [x19]
2624
; A53-NEXT: mov w1, #4
2725
; A53-NEXT: stp x2, x3, [x8, #32]
2826
; A53-NEXT: mov x2, x8
27+
; A53-NEXT: str q0, [x8]
28+
; A53-NEXT: strh w9, [x8, #24]
2929
; A53-NEXT: str wzr, [x8, #20]
3030
; A53-NEXT: bl fcntl
3131
; A53-NEXT: adrp x9, gv0

‎llvm/test/CodeGen/PowerPC/extract-and-store.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -484,8 +484,8 @@ define dso_local void @test_consecutive_i32(<4 x i32> %a, i32* nocapture %b) loc
484484
; CHECK: # %bb.0: # %entry
485485
; CHECK-NEXT: xxsldwi vs0, vs34, vs34, 2
486486
; CHECK-NEXT: li r3, 4
487-
; CHECK-NEXT: stfiwx f0, 0, r5
488487
; CHECK-NEXT: stxsiwx vs34, r5, r3
488+
; CHECK-NEXT: stfiwx f0, 0, r5
489489
; CHECK-NEXT: blr
490490
;
491491
; CHECK-BE-LABEL: test_consecutive_i32:
@@ -501,8 +501,8 @@ define dso_local void @test_consecutive_i32(<4 x i32> %a, i32* nocapture %b) loc
501501
; CHECK-P9: # %bb.0: # %entry
502502
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 2
503503
; CHECK-P9-NEXT: li r3, 4
504-
; CHECK-P9-NEXT: stfiwx f0, 0, r5
505504
; CHECK-P9-NEXT: stxsiwx vs34, r5, r3
505+
; CHECK-P9-NEXT: stfiwx f0, 0, r5
506506
; CHECK-P9-NEXT: blr
507507
;
508508
; CHECK-P9-BE-LABEL: test_consecutive_i32:
@@ -590,33 +590,33 @@ define dso_local void @test_stores_exceed_vec_size(<4 x i32> %a, i32* nocapture
590590
; CHECK-BE-NEXT: li r4, 20
591591
; CHECK-BE-NEXT: stxsiwx vs34, r5, r3
592592
; CHECK-BE-NEXT: xxsldwi vs0, vs34, vs0, 2
593-
; CHECK-BE-NEXT: stxvw4x vs0, 0, r5
594593
; CHECK-BE-NEXT: stfiwx f1, r5, r4
594+
; CHECK-BE-NEXT: stxvw4x vs0, 0, r5
595595
; CHECK-BE-NEXT: blr
596596
;
597597
; CHECK-P9-LABEL: test_stores_exceed_vec_size:
598598
; CHECK-P9: # %bb.0: # %entry
599599
; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
600600
; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l
601601
; CHECK-P9-NEXT: lxvx vs35, 0, r3
602-
; CHECK-P9-NEXT: li r3, 16
603-
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
604602
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1
605-
; CHECK-P9-NEXT: stxv vs35, 0(r5)
603+
; CHECK-P9-NEXT: li r3, 16
606604
; CHECK-P9-NEXT: stfiwx f0, r5, r3
607605
; CHECK-P9-NEXT: li r3, 20
608606
; CHECK-P9-NEXT: stxsiwx vs34, r5, r3
607+
; CHECK-P9-NEXT: vperm v3, v2, v2, v3
608+
; CHECK-P9-NEXT: stxv vs35, 0(r5)
609609
; CHECK-P9-NEXT: blr
610610
;
611611
; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
612612
; CHECK-P9-BE: # %bb.0: # %entry
613613
; CHECK-P9-BE-NEXT: xxspltw vs0, vs34, 0
614614
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs0, 2
615615
; CHECK-P9-BE-NEXT: li r3, 16
616-
; CHECK-P9-BE-NEXT: stxv vs0, 0(r5)
617-
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1
618616
; CHECK-P9-BE-NEXT: stxsiwx vs34, r5, r3
619617
; CHECK-P9-BE-NEXT: li r3, 20
618+
; CHECK-P9-BE-NEXT: stxv vs0, 0(r5)
619+
; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1
620620
; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3
621621
; CHECK-P9-BE-NEXT: blr
622622
entry:
@@ -930,8 +930,8 @@ define void @test_elements_from_two_vec(<4 x i32> %a, <4 x i32> %b, i32* nocaptu
930930
; CHECK-BE: # %bb.0: # %entry
931931
; CHECK-BE-NEXT: xxsldwi vs0, vs34, vs34, 3
932932
; CHECK-BE-NEXT: li r3, 4
933-
; CHECK-BE-NEXT: stfiwx f0, r7, r3
934933
; CHECK-BE-NEXT: stxsiwx vs35, 0, r7
934+
; CHECK-BE-NEXT: stfiwx f0, r7, r3
935935
; CHECK-BE-NEXT: blr
936936
;
937937
; CHECK-P9-LABEL: test_elements_from_two_vec:
@@ -977,19 +977,19 @@ define dso_local void @test_elements_from_three_vec(<4 x float> %a, <4 x float>
977977
; CHECK-BE-NEXT: xxsldwi vs1, vs35, vs35, 1
978978
; CHECK-BE-NEXT: li r3, 4
979979
; CHECK-BE-NEXT: li r4, 8
980+
; CHECK-BE-NEXT: stxsiwx vs36, r9, r4
980981
; CHECK-BE-NEXT: stfiwx f1, r9, r3
981982
; CHECK-BE-NEXT: stfiwx f0, 0, r9
982-
; CHECK-BE-NEXT: stxsiwx vs36, r9, r4
983983
; CHECK-BE-NEXT: blr
984984
;
985985
; CHECK-P9-LABEL: test_elements_from_three_vec:
986986
; CHECK-P9: # %bb.0: # %entry
987987
; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 3
988988
; CHECK-P9-NEXT: li r3, 4
989-
; CHECK-P9-NEXT: stfiwx f0, 0, r9
990-
; CHECK-P9-NEXT: xxsldwi vs0, vs36, vs36, 1
991989
; CHECK-P9-NEXT: stxsiwx vs35, r9, r3
992990
; CHECK-P9-NEXT: li r3, 8
991+
; CHECK-P9-NEXT: stfiwx f0, 0, r9
992+
; CHECK-P9-NEXT: xxsldwi vs0, vs36, vs36, 1
993993
; CHECK-P9-NEXT: stfiwx f0, r9, r3
994994
; CHECK-P9-NEXT: blr
995995
;

‎llvm/test/CodeGen/PowerPC/f128-aggregates.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -353,10 +353,10 @@ define fp128 @sum_float128(i32 signext %count, ...) {
353353
; CHECK-NEXT: addi r3, r1, 40
354354
; CHECK-NEXT: lxvx v3, 0, r3
355355
; CHECK-NEXT: xsaddqp v2, v3, v2
356-
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
357-
; CHECK-NEXT: std [[REG2]], -8(r1)
358356
; CHECK-NEXT: lxv v3, 16(r3)
359357
; CHECK-NEXT: xsaddqp v2, v2, v3
358+
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
359+
; CHECK-NEXT: std [[REG2]], -8(r1)
360360
; CHECK-NEXT: blr
361361
entry:
362362
%ap = alloca i8*, align 8

‎llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -328,27 +328,27 @@ define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x flo
328328
; CHECK-P9-NEXT: lxv vs2, 48(r4)
329329
; CHECK-P9-NEXT: xxswapd vs8, vs2
330330
; CHECK-P9-NEXT: xscvspdpn f8, vs8
331-
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
332-
; CHECK-P9-NEXT: stxv vs5, 32(r3)
333-
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
331+
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
334332
; CHECK-P9-NEXT: xscvspdpn f3, vs3
335333
; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
336334
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
335+
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
336+
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
337+
; CHECK-P9-NEXT: stxv vs6, 64(r3)
337338
; CHECK-P9-NEXT: xscvspdpn f7, vs7
338339
; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
339340
; CHECK-P9-NEXT: xscvspdpn f8, vs2
340341
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
341-
; CHECK-P9-NEXT: stxv vs6, 64(r3)
342-
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
342+
; CHECK-P9-NEXT: xscvspdpn f2, vs2
343+
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
343344
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
344345
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
345-
; CHECK-P9-NEXT: xscvspdpn f2, vs2
346346
; CHECK-P9-NEXT: stxv vs3, 80(r3)
347-
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
348347
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
349-
; CHECK-P9-NEXT: stxv vs2, 112(r3)
350348
; CHECK-P9-NEXT: stxv vs7, 96(r3)
349+
; CHECK-P9-NEXT: stxv vs2, 112(r3)
351350
; CHECK-P9-NEXT: stxv vs4, 48(r3)
351+
; CHECK-P9-NEXT: stxv vs5, 32(r3)
352352
; CHECK-P9-NEXT: stxv vs0, 16(r3)
353353
; CHECK-P9-NEXT: stxv vs1, 0(r3)
354354
; CHECK-P9-NEXT: blr
@@ -738,27 +738,27 @@ define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <1
738738
; CHECK-P9-NEXT: lxv vs2, 48(r4)
739739
; CHECK-P9-NEXT: xxswapd vs8, vs2
740740
; CHECK-P9-NEXT: xscvspdpn f8, vs8
741-
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
742-
; CHECK-P9-NEXT: stxv vs5, 32(r3)
743-
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
741+
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
744742
; CHECK-P9-NEXT: xscvspdpn f3, vs3
745743
; CHECK-P9-NEXT: xxmrghd vs3, vs7, vs3
746744
; CHECK-P9-NEXT: xxsldwi vs7, vs2, vs2, 3
745+
; CHECK-P9-NEXT: xvcvdpuxds vs0, vs0
746+
; CHECK-P9-NEXT: xvcvdpuxds vs6, vs6
747+
; CHECK-P9-NEXT: stxv vs6, 64(r3)
747748
; CHECK-P9-NEXT: xscvspdpn f7, vs7
748749
; CHECK-P9-NEXT: xxmrghd vs7, vs8, vs7
749750
; CHECK-P9-NEXT: xscvspdpn f8, vs2
750751
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
751-
; CHECK-P9-NEXT: stxv vs6, 64(r3)
752-
; CHECK-P9-NEXT: xvcvdpuxds vs4, vs4
752+
; CHECK-P9-NEXT: xscvspdpn f2, vs2
753+
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
753754
; CHECK-P9-NEXT: xvcvdpuxds vs3, vs3
754755
; CHECK-P9-NEXT: xvcvdpuxds vs7, vs7
755-
; CHECK-P9-NEXT: xscvspdpn f2, vs2
756756
; CHECK-P9-NEXT: stxv vs3, 80(r3)
757-
; CHECK-P9-NEXT: xxmrghd vs2, vs8, vs2
758757
; CHECK-P9-NEXT: xvcvdpuxds vs2, vs2
759-
; CHECK-P9-NEXT: stxv vs2, 112(r3)
760758
; CHECK-P9-NEXT: stxv vs7, 96(r3)
759+
; CHECK-P9-NEXT: stxv vs2, 112(r3)
761760
; CHECK-P9-NEXT: stxv vs4, 48(r3)
761+
; CHECK-P9-NEXT: stxv vs5, 32(r3)
762762
; CHECK-P9-NEXT: stxv vs0, 16(r3)
763763
; CHECK-P9-NEXT: stxv vs1, 0(r3)
764764
; CHECK-P9-NEXT: blr

‎llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -712,24 +712,24 @@ define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result,
712712
; CHECK-P9-NEXT: vextsh2d v2, v2
713713
; CHECK-P9-NEXT: xvcvsxddp vs3, v2
714714
; CHECK-P9-NEXT: vperm v2, v4, v4, v3
715+
; CHECK-P9-NEXT: stxv vs2, 32(r3)
715716
; CHECK-P9-NEXT: vextsh2d v2, v2
716717
; CHECK-P9-NEXT: stxv vs3, 48(r3)
718+
; CHECK-P9-NEXT: stxv vs1, 16(r3)
717719
; CHECK-P9-NEXT: xvcvsxddp vs4, v2
718720
; CHECK-P9-NEXT: vperm v2, v4, v4, v5
719721
; CHECK-P9-NEXT: vextsh2d v2, v2
720722
; CHECK-P9-NEXT: xvcvsxddp vs5, v2
721723
; CHECK-P9-NEXT: vperm v2, v4, v4, v0
722724
; CHECK-P9-NEXT: stxv vs4, 64(r3)
723-
; CHECK-P9-NEXT: stxv vs5, 80(r3)
724725
; CHECK-P9-NEXT: vextsh2d v2, v2
725726
; CHECK-P9-NEXT: xvcvsxddp vs6, v2
726727
; CHECK-P9-NEXT: vperm v2, v4, v4, v1
727-
; CHECK-P9-NEXT: vextsh2d v2, v2
728+
; CHECK-P9-NEXT: stxv vs5, 80(r3)
728729
; CHECK-P9-NEXT: stxv vs6, 96(r3)
730+
; CHECK-P9-NEXT: vextsh2d v2, v2
729731
; CHECK-P9-NEXT: xvcvsxddp vs7, v2
730732
; CHECK-P9-NEXT: stxv vs7, 112(r3)
731-
; CHECK-P9-NEXT: stxv vs2, 32(r3)
732-
; CHECK-P9-NEXT: stxv vs1, 16(r3)
733733
; CHECK-P9-NEXT: stxv vs0, 0(r3)
734734
; CHECK-P9-NEXT: blr
735735
;

‎llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -239,18 +239,18 @@ define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i
239239
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
240240
; CHECK-P9-NEXT: xvcvuxdsp vs0, v0
241241
; CHECK-P9-NEXT: lxv v5, 64(r4)
242+
; CHECK-P9-NEXT: stxv v1, 0(r3)
242243
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
243244
; CHECK-P9-NEXT: xvcvuxdsp vs0, v5
244245
; CHECK-P9-NEXT: lxv v4, 80(r4)
245246
; CHECK-P9-NEXT: vpkudum v0, v0, v6
247+
; CHECK-P9-NEXT: stxv v0, 16(r3)
246248
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
247-
; CHECK-P9-NEXT: lxv v3, 96(r4)
248249
; CHECK-P9-NEXT: xvcvuxdsp vs0, v4
250+
; CHECK-P9-NEXT: lxv v3, 96(r4)
249251
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
250252
; CHECK-P9-NEXT: xvcvuxdsp vs0, v3
251253
; CHECK-P9-NEXT: lxv v2, 112(r4)
252-
; CHECK-P9-NEXT: stxv v0, 16(r3)
253-
; CHECK-P9-NEXT: stxv v1, 0(r3)
254254
; CHECK-P9-NEXT: vpkudum v4, v4, v5
255255
; CHECK-P9-NEXT: stxv v4, 32(r3)
256256
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
@@ -275,18 +275,18 @@ define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i
275275
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
276276
; CHECK-BE-NEXT: xvcvuxdsp vs0, v0
277277
; CHECK-BE-NEXT: lxv v5, 80(r4)
278+
; CHECK-BE-NEXT: stxv v1, 0(r3)
278279
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
279280
; CHECK-BE-NEXT: xvcvuxdsp vs0, v5
280281
; CHECK-BE-NEXT: lxv v4, 64(r4)
281282
; CHECK-BE-NEXT: vpkudum v0, v0, v6
283+
; CHECK-BE-NEXT: stxv v0, 16(r3)
282284
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
283-
; CHECK-BE-NEXT: lxv v3, 112(r4)
284285
; CHECK-BE-NEXT: xvcvuxdsp vs0, v4
286+
; CHECK-BE-NEXT: lxv v3, 112(r4)
285287
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
286288
; CHECK-BE-NEXT: xvcvuxdsp vs0, v3
287289
; CHECK-BE-NEXT: lxv v2, 96(r4)
288-
; CHECK-BE-NEXT: stxv v0, 16(r3)
289-
; CHECK-BE-NEXT: stxv v1, 0(r3)
290290
; CHECK-BE-NEXT: vpkudum v4, v4, v5
291291
; CHECK-BE-NEXT: stxv v4, 32(r3)
292292
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3
@@ -532,18 +532,18 @@ define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result,
532532
; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3
533533
; CHECK-P9-NEXT: xvcvsxdsp vs0, v0
534534
; CHECK-P9-NEXT: lxv v5, 64(r4)
535+
; CHECK-P9-NEXT: stxv v1, 0(r3)
535536
; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3
536537
; CHECK-P9-NEXT: xvcvsxdsp vs0, v5
537538
; CHECK-P9-NEXT: lxv v4, 80(r4)
538539
; CHECK-P9-NEXT: vpkudum v0, v0, v6
540+
; CHECK-P9-NEXT: stxv v0, 16(r3)
539541
; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3
540-
; CHECK-P9-NEXT: lxv v3, 96(r4)
541542
; CHECK-P9-NEXT: xvcvsxdsp vs0, v4
543+
; CHECK-P9-NEXT: lxv v3, 96(r4)
542544
; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3
543545
; CHECK-P9-NEXT: xvcvsxdsp vs0, v3
544546
; CHECK-P9-NEXT: lxv v2, 112(r4)
545-
; CHECK-P9-NEXT: stxv v0, 16(r3)
546-
; CHECK-P9-NEXT: stxv v1, 0(r3)
547547
; CHECK-P9-NEXT: vpkudum v4, v4, v5
548548
; CHECK-P9-NEXT: stxv v4, 32(r3)
549549
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3
@@ -568,18 +568,18 @@ define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result,
568568
; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3
569569
; CHECK-BE-NEXT: xvcvsxdsp vs0, v0
570570
; CHECK-BE-NEXT: lxv v5, 80(r4)
571+
; CHECK-BE-NEXT: stxv v1, 0(r3)
571572
; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3
572573
; CHECK-BE-NEXT: xvcvsxdsp vs0, v5
573574
; CHECK-BE-NEXT: lxv v4, 64(r4)
574575
; CHECK-BE-NEXT: vpkudum v0, v0, v6
576+
; CHECK-BE-NEXT: stxv v0, 16(r3)
575577
; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3
576-
; CHECK-BE-NEXT: lxv v3, 112(r4)
577578
; CHECK-BE-NEXT: xvcvsxdsp vs0, v4
579+
; CHECK-BE-NEXT: lxv v3, 112(r4)
578580
; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3
579581
; CHECK-BE-NEXT: xvcvsxdsp vs0, v3
580582
; CHECK-BE-NEXT: lxv v2, 96(r4)
581-
; CHECK-BE-NEXT: stxv v0, 16(r3)
582-
; CHECK-BE-NEXT: stxv v1, 0(r3)
583583
; CHECK-BE-NEXT: vpkudum v4, v4, v5
584584
; CHECK-BE-NEXT: stxv v4, 32(r3)
585585
; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3

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