Merge commit 'f072263e9f62' from llvm.org/main into experimental/cas/main

git apple-llvm automerger · git apple-llvm automerger · commit f1275d67d5ac · 2022-09-12T11:13:23.000+01:00
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2605,8 +2605,7 @@ void UnwrappedLineParser::parseUnbracedBody(bool CheckEOF) {
   FormatToken *Tok = nullptr;
 
   if (Style.InsertBraces && !Line->InPPDirective && !Line->Tokens.empty() &&
-      PreprocessorDirectives.empty()) {
-    assert(!Line->Tokens.empty());
+      PreprocessorDirectives.empty() && FormatTok->isNot(tok::semi)) {
     Tok = Style.BraceWrapping.AfterControlStatement == FormatStyle::BWACS_Never
               ? getLastNonComment(*Line)
               : Line->Tokens.back().Tok;
diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp
@@ -25365,6 +25365,30 @@ TEST_F(FormatTest, InsertBraces) {
                "}",
                Style);
 
+  verifyFormat("do {\n"
+               "#if 0\n"
+               " if (a) {\n"
+               "#else\n"
+               "  if (b) {\n"
+               "#endif\n"
+               "}\n"
+               "}\n"
+               "while (0)\n"
+               "  ;",
+               Style);
+  // TODO: Replace the test above with the one below after #57539 is fixed.
+#if 0
+  verifyFormat("do {\n"
+               "#if 0\n"
+               "  if (a) {\n"
+               "#else\n"
+               "  if (b) {\n"
+               "#endif\n"
+               "  }\n"
+               "} while (0);",
+               Style);
+#endif
+
   Style.ColumnLimit = 15;
 
   verifyFormat("#define A     \\\n"
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -16,6 +16,7 @@
 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
 
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/Optional.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/iterator_range.h"
@@ -523,6 +524,16 @@ class TargetRegisterInfo : public MCRegisterInfo {
   /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
   virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
 
+  /// Returns either a string explaining why the given register is reserved for
+  /// this function, or an empty optional if no explanation has been written.
+  /// The absence of an explanation does not mean that the register is not
+  /// reserved (meaning, you should check that PhysReg is in fact reserved
+  /// before calling this).
+  virtual llvm::Optional<std::string>
+  explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const {
+    return {};
+  }
+
   /// Returns false if we can't guarantee that Physreg, specified as an IR asm
   /// clobber constraint, will be preserved across the statement.
   virtual bool isAsmClobberable(const MachineFunction &MF,
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -411,6 +411,14 @@ void AsmPrinter::emitInlineAsm(const MachineInstr *MI) const {
         LocCookie, Msg, DiagnosticSeverity::DS_Warning));
     MMI->getModule()->getContext().diagnose(
         DiagnosticInfoInlineAsm(LocCookie, Note, DiagnosticSeverity::DS_Note));
+
+    for (const Register RR : RestrRegs) {
+      if (llvm::Optional<std::string> reason =
+              TRI->explainReservedReg(*MF, RR)) {
+        MMI->getModule()->getContext().diagnose(DiagnosticInfoInlineAsm(
+            LocCookie, *reason, DiagnosticSeverity::DS_Note));
+      }
+    }
   }
 
   emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -308,6 +308,16 @@ const uint32_t *AArch64RegisterInfo::getWindowsStackProbePreservedMask() const {
   return CSR_AArch64_StackProbe_Windows_RegMask;
 }
 
+llvm::Optional<std::string>
+AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
+                                        MCRegister PhysReg) const {
+  if (hasBasePointer(MF) &&
+      (PhysReg == AArch64::X19 || PhysReg == AArch64::W19))
+    return std::string("X19 is used as the frame base pointer register.");
+
+  return {};
+}
+
 BitVector
 AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
   const AArch64FrameLowering *TFI = getFrameLowering(MF);
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -91,6 +91,9 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
 
   BitVector getStrictlyReservedRegs(const MachineFunction &MF) const;
   BitVector getReservedRegs(const MachineFunction &MF) const override;
+  llvm::Optional<std::string>
+  explainReservedReg(const MachineFunction &MF,
+                     MCRegister PhysReg) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
   const TargetRegisterClass *
diff --git a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
@@ -1583,8 +1583,11 @@ InductiveRangeCheck::computeSafeIterationSpace(
     bool IsLatchSigned) const {
   // We can deal when types of latch check and range checks don't match in case
   // if latch check is more narrow.
-  auto *IVType = cast<IntegerType>(IndVar->getType());
-  auto *RCType = cast<IntegerType>(getBegin()->getType());
+  auto *IVType = dyn_cast<IntegerType>(IndVar->getType());
+  auto *RCType = dyn_cast<IntegerType>(getBegin()->getType());
+  // Do not work with pointer types.
+  if (!IVType || !RCType)
+    return None;
   if (IVType->getBitWidth() > RCType->getBitWidth())
     return None;
   // IndVar is of the form "A + B * I" (where "I" is the canonical induction
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll b/llvm/test/CodeGen/AArch64/inline-asm-clobber-base-frame-pointer.ll
@@ -0,0 +1,17 @@
+; Check that not only do we warn about clobbering x19 we also say
+; what it is used for.
+
+; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X19
+; CHECK-NEXT: note: Reserved registers on the clobber list
+; CHECK-NEXT: note: X19 is used as the frame base pointer register.
+; CHECK-NEXT: note: X19 is used as the frame base pointer register.
+
+define void @alloca(i64 %size) {
+entry:
+  %a = alloca i128, i64 %size, align 64
+  call void asm sideeffect "nop", "~{x19},~{w19}"()
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/AArch64/rm_redundant_cmp.ll b/llvm/test/CodeGen/AArch64/rm_redundant_cmp.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-linux-gnuabi -O2 | FileCheck %s
 
 ; The following cases are for i16
@@ -9,11 +10,18 @@
 @cost_u_i16 = common global %struct.s_unsigned_i16 zeroinitializer, align 2
 
 define void @test_i16_2cmp_signed_1() {
-; CHECK-LABEL: test_i16_2cmp_signed_1
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.lt
-; CHECK-NOT: cmp
-; CHECK: ret
+; CHECK-LABEL: test_i16_2cmp_signed_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_s_i8_i16
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_s_i8_i16]
+; CHECK-NEXT:    ldrsh w9, [x8, #2]
+; CHECK-NEXT:    ldrsh w10, [x8, #4]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.lt .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %if.end8.sink.split
+; CHECK-NEXT:    strh w9, [x8]
+; CHECK-NEXT:  .LBB0_2: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
   %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
@@ -37,11 +45,21 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i16_2cmp_signed_2() {
-; CHECK-LABEL: test_i16_2cmp_signed_2
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.gt
-; CHECK-NOT: cmp
-; CHECK: b.ge
+; CHECK-LABEL: test_i16_2cmp_signed_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_s_i8_i16
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_s_i8_i16]
+; CHECK-NEXT:    ldrsh w9, [x8, #2]
+; CHECK-NEXT:    ldrsh w10, [x8, #4]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.gt .LBB1_2
+; CHECK-NEXT:  // %bb.1: // %if.else
+; CHECK-NEXT:    mov w9, w10
+; CHECK-NEXT:    b.ge .LBB1_3
+; CHECK-NEXT:  .LBB1_2: // %if.end8.sink.split
+; CHECK-NEXT:    strh w9, [x8]
+; CHECK-NEXT:  .LBB1_3: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2
   %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2
@@ -65,11 +83,18 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i16_2cmp_unsigned_1() {
-; CHECK-LABEL: test_i16_2cmp_unsigned_1
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.lo
-; CHECK-NOT: cmp
-; CHECK: ret
+; CHECK-LABEL: test_i16_2cmp_unsigned_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_u_i16
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_u_i16]
+; CHECK-NEXT:    ldrh w9, [x8, #2]
+; CHECK-NEXT:    ldrh w10, [x8, #4]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.lo .LBB2_2
+; CHECK-NEXT:  // %bb.1: // %if.end8.sink.split
+; CHECK-NEXT:    strh w9, [x8]
+; CHECK-NEXT:  .LBB2_2: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
   %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
@@ -93,11 +118,21 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i16_2cmp_unsigned_2() {
-; CHECK-LABEL: test_i16_2cmp_unsigned_2
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.hi
-; CHECK-NOT: cmp
-; CHECK: b.hs
+; CHECK-LABEL: test_i16_2cmp_unsigned_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_u_i16
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_u_i16]
+; CHECK-NEXT:    ldrh w9, [x8, #2]
+; CHECK-NEXT:    ldrh w10, [x8, #4]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.hi .LBB3_2
+; CHECK-NEXT:  // %bb.1: // %if.else
+; CHECK-NEXT:    mov w9, w10
+; CHECK-NEXT:    b.hs .LBB3_3
+; CHECK-NEXT:  .LBB3_2: // %if.end8.sink.split
+; CHECK-NEXT:    strh w9, [x8]
+; CHECK-NEXT:  .LBB3_3: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2
   %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2
@@ -130,11 +165,18 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 
 
 define void @test_i8_2cmp_signed_1() {
-; CHECK-LABEL: test_i8_2cmp_signed_1
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.lt
-; CHECK-NOT: cmp
-; CHECK: ret
+; CHECK-LABEL: test_i8_2cmp_signed_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_s
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_s]
+; CHECK-NEXT:    ldrsb w9, [x8, #1]
+; CHECK-NEXT:    ldrsb w10, [x8, #2]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.lt .LBB4_2
+; CHECK-NEXT:  // %bb.1: // %if.end8.sink.split
+; CHECK-NEXT:    strb w9, [x8]
+; CHECK-NEXT:  .LBB4_2: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
   %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
@@ -158,11 +200,21 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i8_2cmp_signed_2() {
-; CHECK-LABEL: test_i8_2cmp_signed_2
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.gt
-; CHECK-NOT: cmp
-; CHECK: b.ge
+; CHECK-LABEL: test_i8_2cmp_signed_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_s
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_s]
+; CHECK-NEXT:    ldrsb w9, [x8, #1]
+; CHECK-NEXT:    ldrsb w10, [x8, #2]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.gt .LBB5_2
+; CHECK-NEXT:  // %bb.1: // %if.else
+; CHECK-NEXT:    mov w9, w10
+; CHECK-NEXT:    b.ge .LBB5_3
+; CHECK-NEXT:  .LBB5_2: // %if.end8.sink.split
+; CHECK-NEXT:    strb w9, [x8]
+; CHECK-NEXT:  .LBB5_3: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2
   %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2
@@ -186,11 +238,18 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i8_2cmp_unsigned_1() {
-; CHECK-LABEL: test_i8_2cmp_unsigned_1
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.lo
-; CHECK-NOT: cmp
-; CHECK: ret
+; CHECK-LABEL: test_i8_2cmp_unsigned_1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_u_i8
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_u_i8]
+; CHECK-NEXT:    ldrb w9, [x8, #1]
+; CHECK-NEXT:    ldrb w10, [x8, #2]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.lo .LBB6_2
+; CHECK-NEXT:  // %bb.1: // %if.end8.sink.split
+; CHECK-NEXT:    strb w9, [x8]
+; CHECK-NEXT:  .LBB6_2: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
   %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
@@ -214,11 +273,21 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 }
 
 define void @test_i8_2cmp_unsigned_2() {
-; CHECK-LABEL: test_i8_2cmp_unsigned_2
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK-NEXT: b.hi
-; CHECK-NOT: cmp
-; CHECK: b.hs
+; CHECK-LABEL: test_i8_2cmp_unsigned_2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    adrp x8, :got:cost_u_i8
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:cost_u_i8]
+; CHECK-NEXT:    ldrb w9, [x8, #1]
+; CHECK-NEXT:    ldrb w10, [x8, #2]
+; CHECK-NEXT:    cmp w9, w10
+; CHECK-NEXT:    b.hi .LBB7_2
+; CHECK-NEXT:  // %bb.1: // %if.else
+; CHECK-NEXT:    mov w9, w10
+; CHECK-NEXT:    b.hs .LBB7_3
+; CHECK-NEXT:  .LBB7_2: // %if.end8.sink.split
+; CHECK-NEXT:    strb w9, [x8]
+; CHECK-NEXT:  .LBB7_3: // %if.end8
+; CHECK-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2
   %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2
@@ -247,6 +316,13 @@ if.end8:                                          ; preds = %if.else, %if.then7,
 ; the operand of a set_cc is always a TRUNCATE.
 
 define i1 @foo(float %inl, float %inr) {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    fcvtzs w9, s1
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
   %lval = fptosi float %inl to i8
   %rval = fptosi float %inr to i8
   %sum = icmp eq i8 %lval, %rval
diff --git a/llvm/test/CodeGen/AArch64/typepromotion-cost.ll b/llvm/test/CodeGen/AArch64/typepromotion-cost.ll
diff --git a/llvm/test/Transforms/IRCE/pr40539.ll b/llvm/test/Transforms/IRCE/pr40539.ll
diff --git a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
