[AArch64][GISel] Expand arm64-dup and arm64-rev tests for global isel. NFC

Author: davemgreen

llvm/test/CodeGen/AArch64/arm64-dup.ll

@@ -1,5 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI:       warning: Instruction selection used fallback path for v_shuffledup8
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for v_shuffledup16
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for vduplane8
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for vduplane16
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_perfectshuffle_dupext_v4i16
+; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_perfectshuffle_dupext_v4f16
 
 define <8 x i8> @v_dup8(i8 %A) nounwind {
 ; CHECK-LABEL: v_dup8:
@@ -365,10 +373,19 @@ define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone  {
 ;
 ; *However*, it is a dup vD.4h, vN.h[2*idx].
 define <4 x i16> @test_build_illegal(<4 x i32> %in) {
-; CHECK-LABEL: test_build_illegal:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    dup.4h v0, v0[6]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_build_illegal:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    dup.4h v0, v0[6]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_build_illegal:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov.h v1[1], v0[0]
+; CHECK-GI-NEXT:    mov s0, v0[3]
+; CHECK-GI-NEXT:    mov.h v1[2], v0[0]
+; CHECK-GI-NEXT:    mov.h v1[3], v0[0]
+; CHECK-GI-NEXT:    fmov d0, d1
+; CHECK-GI-NEXT:    ret
   %val = extractelement <4 x i32> %in, i32 3
   %smallval = trunc i32 %val to i16
   %vec = insertelement <4x i16> undef, i16 %smallval, i32 3
@@ -380,10 +397,16 @@ define <4 x i16> @test_build_illegal(<4 x i32> %in) {
 ; SelectionDAGBuilder here. We then added a DUPLANE on top of that, preventing
 ; the formation of an indexed-by-7 MLS.
 define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
-; CHECK-LABEL: test_high_splat:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mls.4h v0, v1, v2[7]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_high_splat:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    mls.4h v0, v1, v2[7]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_high_splat:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    dup.8h v2, v2[7]
+; CHECK-GI-NEXT:    mls.4h v0, v2, v1
+; CHECK-GI-NEXT:    ret
 entry:
   %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
   %mul = mul <4 x i16> %shuffle, %b
@@ -418,34 +441,65 @@ define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b
 }
 
 define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: test_perfectshuffle_dupext_v4i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    trn1.4s v0, v0, v0
-; CHECK-NEXT:    mov.d v0[1], v1[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_perfectshuffle_dupext_v4i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    trn1.4s v0, v0, v0
+; CHECK-SD-NEXT:    mov.d v0[1], v1[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_perfectshuffle_dupext_v4i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI35_0
+; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI35_0]
+; CHECK-GI-NEXT:    tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT:    ret
   %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
   ret <4 x i32> %r
 }
 
 define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind {
-; CHECK-LABEL: test_perfectshuffle_dupext_v4f32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    trn1.4s v0, v0, v0
-; CHECK-NEXT:    mov.d v0[1], v1[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: test_perfectshuffle_dupext_v4f32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    trn1.4s v0, v0, v0
+; CHECK-SD-NEXT:    mov.d v0[1], v1[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_perfectshuffle_dupext_v4f32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI36_0
+; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
+; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI36_0]
+; CHECK-GI-NEXT:    tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT:    ret
   %r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 4, i32 5>
   ret <4 x float> %r
 }
 
 define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
-; CHECK-LABEL: disguised_dup:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext.16b v1, v0, v0, #4
-; CHECK-NEXT:    mov.s v1[2], v0[0]
-; CHECK-NEXT:    dup.4s v0, v0[0]
-; CHECK-NEXT:    str q1, [x0]
-; CHECK-NEXT:    str q0, [x1]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: disguised_dup:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ext.16b v1, v0, v0, #4
+; CHECK-SD-NEXT:    mov.s v1[2], v0[0]
+; CHECK-SD-NEXT:    dup.4s v0, v0[0]
+; CHECK-SD-NEXT:    str q1, [x0]
+; CHECK-SD-NEXT:    str q0, [x1]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: disguised_dup:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI37_1
+; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 def $q0_q1
+; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI37_1]
+; CHECK-GI-NEXT:    adrp x8, .LCPI37_0
+; CHECK-GI-NEXT:    tbl.16b v0, { v0, v1 }, v2
+; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI37_0]
+; CHECK-GI-NEXT:    tbl.16b v2, { v0, v1 }, v2
+; CHECK-GI-NEXT:    str q0, [x0]
+; CHECK-GI-NEXT:    str q2, [x1]
+; CHECK-GI-NEXT:    ret
   %shuf = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 0, i32 0>
   %dup = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 2, i32 3>
   store <4 x float> %shuf, ptr %p1, align 8
@@ -454,42 +508,71 @@ define void @disguised_dup(<4 x float> %x, ptr %p1, ptr %p2) {
 }
 
 define <2 x i32> @dup_const2(<2 x i32> %A) nounwind {
-; CHECK-LABEL: dup_const2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32770
-; CHECK-NEXT:    movk w8, #128, lsl #16
-; CHECK-NEXT:    dup.2s v1, w8
-; CHECK-NEXT:    add.2s v0, v0, v1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: dup_const2:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #32770 // =0x8002
+; CHECK-SD-NEXT:    movk w8, #128, lsl #16
+; CHECK-SD-NEXT:    dup.2s v1, w8
+; CHECK-SD-NEXT:    add.2s v0, v0, v1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: dup_const2:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI38_0
+; CHECK-GI-NEXT:    ldr d1, [x8, :lo12:.LCPI38_0]
+; CHECK-GI-NEXT:    add.2s v0, v0, v1
+; CHECK-GI-NEXT:    ret
   %tmp2 = add <2 x i32> %A, <i32 8421378, i32 8421378>
   ret <2 x i32> %tmp2
 }
 
 define <2 x i32> @dup_const4_ext(<4 x i32> %A) nounwind {
-; CHECK-LABEL: dup_const4_ext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32769
-; CHECK-NEXT:    movk w8, #128, lsl #16
-; CHECK-NEXT:    dup.2s v1, w8
-; CHECK-NEXT:    add.2s v0, v0, v1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: dup_const4_ext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #32769 // =0x8001
+; CHECK-SD-NEXT:    movk w8, #128, lsl #16
+; CHECK-SD-NEXT:    dup.2s v1, w8
+; CHECK-SD-NEXT:    add.2s v0, v0, v1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: dup_const4_ext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI39_0
+; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI39_0]
+; CHECK-GI-NEXT:    add.4s v0, v0, v1
+; CHECK-GI-NEXT:    ext.16b v0, v0, v0, #0
+; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT:    ret
   %tmp1 = add <4 x i32> %A, <i32 8421377, i32 8421377, i32 8421377, i32 8421377>
   %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   ret <2 x i32> %tmp2
 }
 
 define <4 x i32> @dup_const24(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C) nounwind {
-; CHECK-LABEL: dup_const24:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32768
-; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    movk w8, #128, lsl #16
-; CHECK-NEXT:    dup.4s v3, w8
-; CHECK-NEXT:    add.2s v0, v0, v3
-; CHECK-NEXT:    mov.d v0[1], v1[0]
-; CHECK-NEXT:    add.4s v1, v2, v3
-; CHECK-NEXT:    eor.16b v0, v1, v0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: dup_const24:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #32768 // =0x8000
+; CHECK-SD-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-SD-NEXT:    movk w8, #128, lsl #16
+; CHECK-SD-NEXT:    dup.4s v3, w8
+; CHECK-SD-NEXT:    add.2s v0, v0, v3
+; CHECK-SD-NEXT:    mov.d v0[1], v1[0]
+; CHECK-SD-NEXT:    add.4s v1, v2, v3
+; CHECK-SD-NEXT:    eor.16b v0, v1, v0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: dup_const24:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI40_1
+; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
+; CHECK-GI-NEXT:    ldr d3, [x8, :lo12:.LCPI40_1]
+; CHECK-GI-NEXT:    adrp x8, .LCPI40_0
+; CHECK-GI-NEXT:    add.2s v0, v0, v3
+; CHECK-GI-NEXT:    ldr q3, [x8, :lo12:.LCPI40_0]
+; CHECK-GI-NEXT:    mov.d v0[1], v1[0]
+; CHECK-GI-NEXT:    add.4s v1, v2, v3
+; CHECK-GI-NEXT:    eor.16b v0, v1, v0
+; CHECK-GI-NEXT:    ret
   %tmp1 = add <2 x i32> %A, <i32 8421376, i32 8421376>
   %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %tmp3 = add <4 x i32> %C, <i32 8421376, i32 8421376, i32 8421376, i32 8421376>
@@ -498,10 +581,16 @@ define <4 x i32> @dup_const24(<2 x i32> %A, <2 x i32> %B, <4 x i32> %C) nounwind
 }
 
 define <8 x i16> @bitcast_i64_v8i16(i64 %a) {
-; CHECK-LABEL: bitcast_i64_v8i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    dup.8h v0, w0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: bitcast_i64_v8i16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    dup.8h v0, w0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: bitcast_i64_v8i16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fmov d0, x0
+; CHECK-GI-NEXT:    dup.8h v0, v0[0]
+; CHECK-GI-NEXT:    ret
   %b = bitcast i64 %a to <4 x i16>
   %r = shufflevector <4 x i16> %b, <4 x i16> poison, <8 x i32> zeroinitializer
   ret <8 x i16> %r
@@ -541,11 +630,16 @@ define <8 x half> @bitcast_i64_v8f16(i64 %a) {
 }
 
 define <2 x i64> @bitcast_i64_v2f64(i64 %a) {
-; CHECK-LABEL: bitcast_i64_v2f64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fmov d0, x0
-; CHECK-NEXT:    dup.2d v0, v0[0]
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: bitcast_i64_v2f64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    fmov d0, x0
+; CHECK-SD-NEXT:    dup.2d v0, v0[0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: bitcast_i64_v2f64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    dup.2d v0, x0
+; CHECK-GI-NEXT:    ret
   %b = bitcast i64 %a to <1 x i64>
   %r = shufflevector <1 x i64> %b, <1 x i64> poison, <2 x i32> zeroinitializer
   ret <2 x i64> %r