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[IR] IRBuilderBase::CreateOr(): fix short-circuiting for constant on LHS
There is no guarantee that the constant is on RHS here, we have to handle both cases. Refs. https://reviews.llvm.org/D109368#3089809
1 parent ab1dbce commit f3df87d

16 files changed

+594
-620
lines changed

‎clang/test/CodeGenCXX/cfi-mfcall.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,8 @@ void f(S *s, void (S::*p)()) {
2525

2626
// CHECK: [[NVFPTR:%.*]] = bitcast void (%struct.S*)* {{.*}} to i8*
2727
// CHECK: [[TT1:%.*]] = call i1 @llvm.type.test(i8* [[NVFPTR]], metadata !"_ZTSM2B1FvvE")
28-
// CHECK: [[OR1:%.*]] = or i1 false, [[TT1]]
2928
// CHECK: [[TT2:%.*]] = call i1 @llvm.type.test(i8* [[NVFPTR]], metadata !"_ZTSM2B2FvvE")
30-
// CHECK: [[OR2:%.*]] = or i1 [[OR1]], [[TT2]]
29+
// CHECK: [[OR2:%.*]] = or i1 [[TT1]], [[TT2]]
3130
// CHECK: br i1 [[OR2]], label {{.*}}, label %[[TRAP2:[^,]*]]
3231

3332
// CHECK: [[TRAP2]]:

‎llvm/include/llvm/IR/IRBuilder.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1386,6 +1386,8 @@ class IRBuilderBase {
13861386
}
13871387

13881388
Value *CreateOr(Value *LHS, Value *RHS, const Twine &Name = "") {
1389+
if (!isa<Constant>(RHS) && isa<Constant>(LHS))
1390+
std::swap(LHS, RHS);
13891391
if (auto *RC = dyn_cast<Constant>(RHS)) {
13901392
if (RC->isNullValue())
13911393
return LHS; // LHS | 0 -> LHS

‎llvm/test/Instrumentation/BoundsChecking/opt.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ for.body.i: ; preds = %for.body.i, %entry
5050
; CHECK: mul i64 {{.*}}, 4
5151
; CHECK: sub i64 4000, %
5252
; CHECK-NEXT: icmp ult i64 {{.*}}, 4
53-
; CHECK-NEXT: or i1
5453
; CHECK: trap
5554
%1 = load i32, i32* %arrayidx.i, align 4
5655
%add.i = add nsw i32 %1, %sum.01.i
@@ -243,7 +242,6 @@ for.body4: ; preds = %for.body4, %for.con
243242
; CHECK: add i64
244243
; CHECK: sub i64 16, %
245244
; CHECK-NEXT: icmp ult i64 {{.*}}, 4
246-
; CHECK-NEXT: or i1
247245
; CHECK: trap
248246
%1 = load i32, i32* %arrayidx7, align 4
249247
%add = add nsw i32 %1, %sum.119

‎llvm/test/Transforms/LoopDistribute/scev-inserted-runtime-check.ll

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -24,18 +24,17 @@ define void @f(i32* noalias %a, i32* noalias %b, i32* noalias %c, i32* noalias %
2424
; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
2525
; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
2626
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]
27-
; CHECK-NEXT: [[TMP9:%.*]] = or i1 false, [[TMP8]]
2827
; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])
2928
; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
3029
; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
31-
; CHECK-NEXT: [[TMP10:%.*]] = sub i64 0, [[MUL_RESULT3]]
32-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
33-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP10]]
34-
; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i8* [[TMP12]], [[A5]]
35-
; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i8* [[TMP11]], [[A5]]
36-
; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW4]]
37-
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP9]], [[TMP15]]
38-
; CHECK-NEXT: br i1 [[TMP16]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]
30+
; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]
31+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* [[A5]], i64 [[MUL_RESULT3]]
32+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* [[A5]], i64 [[TMP9]]
33+
; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], [[A5]]
34+
; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], [[A5]]
35+
; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]
36+
; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]
37+
; CHECK-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]
3938
; CHECK: for.body.ph.lver.orig:
4039
; CHECK-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]
4140
; CHECK: for.body.lver.orig:
@@ -171,18 +170,17 @@ define void @f_with_offset(i32* noalias %b, i32* noalias %c, i32* noalias %d, i3
171170
; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
172171
; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
173172
; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]
174-
; CHECK-NEXT: [[TMP9:%.*]] = or i1 false, [[TMP8]]
175173
; CHECK-NEXT: [[MUL2:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 8, i64 [[TMP0]])
176174
; CHECK-NEXT: [[MUL_RESULT3:%.*]] = extractvalue { i64, i1 } [[MUL2]], 0
177175
; CHECK-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
178-
; CHECK-NEXT: [[TMP10:%.*]] = sub i64 0, [[MUL_RESULT3]]
179-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[MUL_RESULT3]]
180-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[TMP10]]
181-
; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i8* [[TMP12]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)
182-
; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i8* [[TMP11]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)
183-
; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP14]], [[MUL_OVERFLOW4]]
184-
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP9]], [[TMP15]]
185-
; CHECK-NEXT: br i1 [[TMP16]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]
176+
; CHECK-NEXT: [[TMP9:%.*]] = sub i64 0, [[MUL_RESULT3]]
177+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[MUL_RESULT3]]
178+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, i8* bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*), i64 [[TMP9]]
179+
; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i8* [[TMP11]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)
180+
; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i8* [[TMP10]], bitcast (i32* getelementptr inbounds ([8192 x i32], [8192 x i32]* @global_a, i64 0, i64 42) to i8*)
181+
; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]
182+
; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP8]], [[TMP14]]
183+
; CHECK-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH_LDIST1:%.*]]
186184
; CHECK: for.body.ph.lver.orig:
187185
; CHECK-NEXT: br label [[FOR_BODY_LVER_ORIG:%.*]]
188186
; CHECK: for.body.lver.orig:

‎llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll

Lines changed: 36 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -84,31 +84,30 @@ define void @test_stride-1_4i32(i32* readonly %data, i32* noalias nocapture %dst
8484
; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 2
8585
; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP1]], 2
8686
; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[MUL_OVERFLOW]]
87-
; CHECK-NEXT: [[TMP6:%.*]] = or i1 false, [[TMP5]]
88-
; CHECK-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
87+
; CHECK-NEXT: br i1 [[TMP5]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
8988
; CHECK: vector.ph:
9089
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N]], 4
9190
; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]]
9291
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
9392
; CHECK: vector.body:
9493
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
95-
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[INDEX]], 0
96-
; CHECK-NEXT: [[TMP8:%.*]] = mul nuw nsw i32 [[TMP7]], -1
97-
; CHECK-NEXT: [[TMP9:%.*]] = add nuw nsw i32 [[TMP8]], 2
98-
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP9]]
99-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 0
100-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i32 -3
101-
; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP12]] to <4 x i32>*
102-
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP13]], align 4
94+
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 0
95+
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw i32 [[TMP6]], -1
96+
; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i32 [[TMP7]], 2
97+
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP8]]
98+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP9]], i32 0
99+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 -3
100+
; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP11]] to <4 x i32>*
101+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP12]], align 4
103102
; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
104-
; CHECK-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[REVERSE]]
105-
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP7]]
106-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 0
107-
; CHECK-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP16]] to <4 x i32>*
108-
; CHECK-NEXT: store <4 x i32> [[TMP14]], <4 x i32>* [[TMP17]], align 4
103+
; CHECK-NEXT: [[TMP13:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[REVERSE]]
104+
; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP6]]
105+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 0
106+
; CHECK-NEXT: [[TMP16:%.*]] = bitcast i32* [[TMP15]] to <4 x i32>*
107+
; CHECK-NEXT: store <4 x i32> [[TMP13]], <4 x i32>* [[TMP16]], align 4
109108
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
110-
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
111-
; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
109+
; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
110+
; CHECK-NEXT: br i1 [[TMP17]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
112111
; CHECK: middle.block:
113112
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
114113
; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]]
@@ -120,8 +119,8 @@ define void @test_stride-1_4i32(i32* readonly %data, i32* noalias nocapture %dst
120119
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[I_023]], -1
121120
; CHECK-NEXT: [[ADD5:%.*]] = add nuw nsw i32 [[MUL]], 2
122121
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[DATA]], i32 [[ADD5]]
123-
; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
124-
; CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 5, [[TMP19]]
122+
; CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
123+
; CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 5, [[TMP18]]
125124
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[DST]], i32 [[I_023]]
126125
; CHECK-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX9]], align 4
127126
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_023]], 1
@@ -358,8 +357,7 @@ define void @test_stride_loopinvar_4i32(i32* readonly %data, i32* noalias nocapt
358357
; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
359358
; CHECK: vector.scevcheck:
360359
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STRIDE:%.*]], 1
361-
; CHECK-NEXT: [[TMP0:%.*]] = or i1 false, [[IDENT_CHECK]]
362-
; CHECK-NEXT: br i1 [[TMP0]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
360+
; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
363361
; CHECK: vector.ph:
364362
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i32 [[N:%.*]], 3
365363
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], 4
@@ -370,22 +368,22 @@ define void @test_stride_loopinvar_4i32(i32* readonly %data, i32* noalias nocapt
370368
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[INDEX]], i32 0
371369
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
372370
; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
373-
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0
374-
; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP1]], i32 [[N]])
375-
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i32 [[TMP1]], [[STRIDE]]
376-
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 2
377-
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP3]]
378-
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 0
379-
; CHECK-NEXT: [[TMP6:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
380-
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP6]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> poison)
381-
; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_LOAD]]
382-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP1]]
383-
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 0
384-
; CHECK-NEXT: [[TMP10:%.*]] = bitcast i32* [[TMP9]] to <4 x i32>*
385-
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP7]], <4 x i32>* [[TMP10]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
371+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
372+
; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP0]], i32 [[N]])
373+
; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[TMP0]], [[STRIDE]]
374+
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 2
375+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[DATA:%.*]], i32 [[TMP2]]
376+
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 0
377+
; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[TMP4]] to <4 x i32>*
378+
; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[TMP5]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]], <4 x i32> poison)
379+
; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> <i32 5, i32 5, i32 5, i32 5>, [[WIDE_MASKED_LOAD]]
380+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i32 [[TMP0]]
381+
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 0
382+
; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32* [[TMP8]] to <4 x i32>*
383+
; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP6]], <4 x i32>* [[TMP9]], i32 4, <4 x i1> [[ACTIVE_LANE_MASK]])
386384
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
387-
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
388-
; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
385+
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
386+
; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
389387
; CHECK: middle.block:
390388
; CHECK-NEXT: br i1 true, label [[END:%.*]], label [[SCALAR_PH]]
391389
; CHECK: scalar.ph:
@@ -396,8 +394,8 @@ define void @test_stride_loopinvar_4i32(i32* readonly %data, i32* noalias nocapt
396394
; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[I_023]], [[STRIDE]]
397395
; CHECK-NEXT: [[ADD5:%.*]] = add nuw nsw i32 [[MUL]], 2
398396
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[DATA]], i32 [[ADD5]]
399-
; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
400-
; CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 5, [[TMP12]]
397+
; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
398+
; CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 5, [[TMP11]]
401399
; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[DST]], i32 [[I_023]]
402400
; CHECK-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX9]], align 4
403401
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_023]], 1

‎llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll

Lines changed: 22 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -282,32 +282,31 @@ define void @strides_different_direction(i32* noalias nocapture %A, i32* noalias
282282
; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], [[N]]
283283
; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP0]], [[N]]
284284
; CHECK-NEXT: [[TMP4:%.*]] = or i1 [[TMP2]], [[MUL_OVERFLOW]]
285-
; CHECK-NEXT: [[TMP5:%.*]] = or i1 false, [[TMP4]]
286-
; CHECK-NEXT: br i1 [[TMP5]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
285+
; CHECK-NEXT: br i1 [[TMP4]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
287286
; CHECK: vector.ph:
288287
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
289288
; CHECK: vector.body:
290289
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
291-
; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[INDEX]], 0
292-
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 [[TMP6]]
293-
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 0
294-
; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32* [[TMP8]] to <4 x i32>*
295-
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP9]], align 4
296-
; CHECK-NEXT: [[TMP10:%.*]] = sub nsw i32 [[N]], [[TMP6]]
297-
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i32 [[TMP10]]
298-
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i32 0
299-
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP12]], i32 -3
300-
; CHECK-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP13]] to <4 x i32>*
301-
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP14]], align 4
290+
; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[INDEX]], 0
291+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 [[TMP5]]
292+
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i32 0
293+
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*
294+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP8]], align 4
295+
; CHECK-NEXT: [[TMP9:%.*]] = sub nsw i32 [[N]], [[TMP5]]
296+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i32 [[TMP9]]
297+
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i32 0
298+
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i32 -3
299+
; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP12]] to <4 x i32>*
300+
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP13]], align 4
302301
; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i32> [[WIDE_LOAD1]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
303-
; CHECK-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[REVERSE]], [[WIDE_LOAD]]
304-
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP6]]
305-
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP16]], i32 0
306-
; CHECK-NEXT: [[TMP18:%.*]] = bitcast i32* [[TMP17]] to <4 x i32>*
307-
; CHECK-NEXT: store <4 x i32> [[TMP15]], <4 x i32>* [[TMP18]], align 4
302+
; CHECK-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[REVERSE]], [[WIDE_LOAD]]
303+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP5]]
304+
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 0
305+
; CHECK-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP16]] to <4 x i32>*
306+
; CHECK-NEXT: store <4 x i32> [[TMP14]], <4 x i32>* [[TMP17]], align 4
308307
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
309-
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[INDEX_NEXT]], 428
310-
; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
308+
; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], 428
309+
; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
311310
; CHECK: middle.block:
312311
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 431, 428
313312
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
@@ -319,11 +318,11 @@ define void @strides_different_direction(i32* noalias nocapture %A, i32* noalias
319318
; CHECK: for.body:
320319
; CHECK-NEXT: [[I_09:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[ADD3:%.*]], [[FOR_BODY]] ]
321320
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[I_09]]
322-
; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
321+
; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
323322
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[N]], [[I_09]]
324323
; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[C]], i32 [[SUB]]
325-
; CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
326-
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
324+
; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
325+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP19]]
327326
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[I_09]]
328327
; CHECK-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX2]], align 4
329328
; CHECK-NEXT: [[ADD3]] = add nuw nsw i32 [[I_09]], 1

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