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[RISCV] Add SiFive X390 scheduling model (llvm#143938)
This patch adds the scheduling model for sifive-x390. X390 is a dual issue in-order CPU. It has two scalar and two vector pipes, with VLEN=1024 and DLEN=512. Co-authored-by: Michael Maitland <[email protected]>
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11 files changed

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-163
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11 files changed

+10225
-163
lines changed

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -292,7 +292,8 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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FeatureStdExtZbb],
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SiFiveIntelligenceTuneFeatures>;
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def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", NoSchedModel,
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def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390",
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SiFiveX390Model,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtM,

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

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‎llvm/test/tools/llvm-mca/RISCV/SiFiveX390/div-fdiv.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s \
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# RUN: | FileCheck %s
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div a0, a1, a2
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fdiv.s f1, f2, f3
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:1
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# CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
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# CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:1
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# CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:1
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# CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:1
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# CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 66 65.00 66 VLEN1024X300SiFive7IDiv[65],VLEN1024X300SiFive7PipeAB,VLEN1024X300SiFive7PipeB DIV div a0, a1, a2
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# CHECK-NEXT: 1 27 26.00 27 VLEN1024X300SiFive7FDiv[26],VLEN1024X300SiFive7PipeAB,VLEN1024X300SiFive7PipeB FDIV_S fdiv.s ft1, ft2, ft3
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN1024X300SiFive7VA1
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# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA2
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# CHECK-NEXT: [6] - VLEN1024X300SiFive7VCQ
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# CHECK-NEXT: [7] - VLEN1024X300SiFive7VL
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# CHECK-NEXT: [8] - VLEN1024X300SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
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# CHECK-NEXT: 26.00 65.00 - 2.00 - - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
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# CHECK-NEXT: - 65.00 - 1.00 - - - - - div a0, a1, a2
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# CHECK-NEXT: 26.00 - - 1.00 - - - - - fdiv.s ft1, ft2, ft3

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s

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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
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# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
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# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
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# SPEC.
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vsetvli zero, zero, e32, mf2, tu, mu
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vdiv.vv v12, v12, v12
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vsetvli zero, zero, e8, mf8, tu, mu
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vdiv.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN1024X300SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA1:1
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# CHECK-NEXT: [6] - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
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# CHECK-NEXT: [7] - VLEN1024X300SiFive7VA2:1
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# CHECK-NEXT: [8] - VLEN1024X300SiFive7VCQ:1
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# CHECK-NEXT: [9] - VLEN1024X300SiFive7VL:1
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# CHECK-NEXT: [10] - VLEN1024X300SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
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# CHECK-NEXT: 1 112 112.00 112 VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv v12, v12, v12
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
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# CHECK-NEXT: 1 60 60.00 60 VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv v12, v12, v12
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN1024X300SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN1024X300SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN1024X300SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN1024X300SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN1024X300SiFive7VA1
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# CHECK-NEXT: [5] - VLEN1024X300SiFive7VA2
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# CHECK-NEXT: [6] - VLEN1024X300SiFive7VCQ
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# CHECK-NEXT: [7] - VLEN1024X300SiFive7VL
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# CHECK-NEXT: [8] - VLEN1024X300SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8]
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# CHECK-NEXT: - - 2.00 - 174.00 - 2.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
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# CHECK-NEXT: - - - - 113.00 - 1.00 - - vdiv.vv v12, v12, v12
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# CHECK-NEXT: - - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
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# CHECK-NEXT: - - - - 61.00 - 1.00 - - vdiv.vv v12, v12, v12

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