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[RISCV] Add Xqcibi Select_GPR_Using_CC_<Imm> Pseudos to isSelectPseudo (llvm#140698)
Not adding them was leading to a crash when trying to expand these pseudo instructions. I've also fixed the register class types for the Xqcibi instructions in these pseudo instructions which was incorrect and was exposed by the machine verifier while running the test case added in this patch. Fixes llvm#140697
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-32
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6 files changed

+67
-32
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21032,7 +21032,11 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
2103221032

2103321033
auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
2103421034
if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
21035-
MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5) &&
21035+
MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5_CV &&
21036+
MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC &&
21037+
MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC &&
21038+
MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC &&
21039+
MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC) &&
2103621040
Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
2103721041
Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
2103821042
Next->getOperand(5).isKill())
@@ -21365,11 +21369,11 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2136521369
"ReadCounterWide is only to be used on riscv32");
2136621370
return emitReadCounterWidePseudo(MI, BB);
2136721371
case RISCV::Select_GPR_Using_CC_GPR:
21368-
case RISCV::Select_GPR_Using_CC_SImm5:
21369-
case RISCV::Select_GPR_Using_CC_SImm5NonZero:
21370-
case RISCV::Select_GPR_Using_CC_UImm5NonZero:
21371-
case RISCV::Select_GPR_Using_CC_SImm16NonZero:
21372-
case RISCV::Select_GPR_Using_CC_UImm16NonZero:
21372+
case RISCV::Select_GPR_Using_CC_SImm5_CV:
21373+
case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
21374+
case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
21375+
case RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC:
21376+
case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
2137321377
case RISCV::Select_FPR16_Using_CC_GPR:
2137421378
case RISCV::Select_FPR16INX_Using_CC_GPR:
2137521379
case RISCV::Select_FPR32_Using_CC_GPR:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1648,9 +1648,9 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
16481648

16491649
multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
16501650
let usesCustomInserter = 1 in
1651-
def Select_GPR_Using_ # NAME
1651+
def Select_# valty #_Using_ # NAME
16521652
: Pseudo<(outs valty:$dst),
1653-
(ins GPR:$lhs, imm:$imm, cond_code:$cc,
1653+
(ins valty:$lhs, imm:$imm, cond_code:$cc,
16541654
valty:$truev, valty:$falsev), []>;
16551655
}
16561656

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -802,12 +802,12 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
802802
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
803803
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
804804

805-
defm CC_SImm5 : SelectCC_GPR_riirr<GPR, simm5>;
805+
defm CC_SImm5_CV : SelectCC_GPR_riirr<GPR, simm5>;
806806

807807
class Selectbi<CondCode Cond>
808808
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
809809
(i32 GPR:$truev), GPR:$falsev),
810-
(Select_GPR_Using_CC_SImm5 GPR:$lhs, simm5:$Constant,
810+
(Select_GPR_Using_CC_SImm5_CV GPR:$lhs, simm5:$Constant,
811811
(IntCCtoRISCVCCCV $cc), GPR:$truev, GPR:$falsev)>;
812812

813813
def : Selectbi<SETEQ>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1327,16 +1327,16 @@ class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
13271327
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
13281328
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
13291329

1330-
defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPR, simm5nonzero>;
1331-
defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPR, uimm5nonzero>;
1332-
defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPR, simm16nonzero>;
1333-
defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPR, uimm16nonzero>;
1330+
defm CC_SImm5NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, simm5nonzero>;
1331+
defm CC_UImm5NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, uimm5nonzero>;
1332+
defm CC_SImm16NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, simm16nonzero>;
1333+
defm CC_UImm16NonZero_QC : SelectCC_GPR_riirr<GPRNoX0, uimm16nonzero>;
13341334

13351335
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
1336-
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
1337-
(i32 GPR:$truev), GPR:$falsev),
1338-
(OpNode GPR:$lhs, InTyImm:$Constant,
1339-
(IntCCtoQCRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
1336+
: Pat<(riscv_selectcc_frag:$cc (i32 GPRNoX0:$lhs), InTyImm:$Constant, Cond,
1337+
(i32 GPRNoX0:$truev), GPRNoX0:$falsev),
1338+
(OpNode GPRNoX0:$lhs, InTyImm:$Constant,
1339+
(IntCCtoQCRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;
13401340

13411341
/// Simple arithmetic operations
13421342

@@ -1409,19 +1409,19 @@ def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
14091409
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
14101410
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
14111411

1412-
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1413-
def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1414-
def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1415-
def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1416-
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
1417-
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
1418-
1419-
def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1420-
def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1421-
def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1422-
def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1423-
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
1424-
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
1412+
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1413+
def : SelectQCbi<SETNE, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1414+
def : SelectQCbi<SETLT, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1415+
def : SelectQCbi<SETGE, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
1416+
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPRNoX0_Using_CC_UImm5NonZero_QC>;
1417+
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPRNoX0_Using_CC_UImm5NonZero_QC>;
1418+
1419+
def : SelectQCbi<SETEQ, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1420+
def : SelectQCbi<SETNE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1421+
def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1422+
def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
1423+
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
1424+
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
14251425
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
14261426

14271427
let Predicates = [HasVendorXqcibm, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,11 @@ def isSelectPseudo
4949
MCReturnStatement<
5050
CheckOpcode<[
5151
Select_GPR_Using_CC_GPR,
52-
Select_GPR_Using_CC_SImm5,
52+
Select_GPR_Using_CC_SImm5_CV,
53+
Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
54+
Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
55+
Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
56+
Select_GPRNoX0_Using_CC_UImm16NonZero_QC,
5357
Select_FPR16_Using_CC_GPR,
5458
Select_FPR16INX_Using_CC_GPR,
5559
Select_FPR32_Using_CC_GPR,

‎llvm/test/CodeGen/RISCV/xqcibi.ll

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -355,5 +355,32 @@ t:
355355
ret i32 1
356356
}
357357

358+
define i1 @selectcc(i64 %0) {
359+
; RV32I-LABEL: selectcc:
360+
; RV32I: # %bb.0: # %entry
361+
; RV32I-NEXT: li a2, 512
362+
; RV32I-NEXT: beq a1, a2, .LBB12_2
363+
; RV32I-NEXT: # %bb.1: # %entry
364+
; RV32I-NEXT: sltiu a0, a1, 513
365+
; RV32I-NEXT: xori a0, a0, 1
366+
; RV32I-NEXT: ret
367+
; RV32I-NEXT: .LBB12_2:
368+
; RV32I-NEXT: snez a0, a0
369+
; RV32I-NEXT: ret
370+
;
371+
; RV32IXQCIBI-LABEL: selectcc:
372+
; RV32IXQCIBI: # %bb.0: # %entry
373+
; RV32IXQCIBI-NEXT: qc.e.beqi a1, 512, .LBB12_2
374+
; RV32IXQCIBI-NEXT: # %bb.1: # %entry
375+
; RV32IXQCIBI-NEXT: sltiu a0, a1, 513
376+
; RV32IXQCIBI-NEXT: xori a0, a0, 1
377+
; RV32IXQCIBI-NEXT: ret
378+
; RV32IXQCIBI-NEXT: .LBB12_2:
379+
; RV32IXQCIBI-NEXT: snez a0, a0
380+
; RV32IXQCIBI-NEXT: ret
381+
entry:
382+
%cmp10.i = icmp ugt i64 %0, 2199023255552
383+
ret i1 %cmp10.i
384+
}
358385

359386
!0 = !{!"branch_weights", i32 1, i32 99}

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