Skip to content

Commit f833edf

Browse files
committed
[clang] Define SwiftInfo for RISCVTargetCodeGenInfo (llvm#82152)
For Embedded Swift, let's unblock building for RISC-V boards (e.g. ESP32-C6). This isn't trying to add full RISC-V support to Swift / Embedded Swift, it's just fixing the immediate blocker (not having SwiftInfo defined blocks all compilations).
1 parent ae573f7 commit f833edf

File tree

2 files changed

+8
-1
lines changed

2 files changed

+8
-1
lines changed

clang/lib/CodeGen/Targets/RISCV.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -500,7 +500,10 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
500500
public:
501501
RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
502502
unsigned FLen)
503-
: TargetCodeGenInfo(std::make_unique<RISCVABIInfo>(CGT, XLen, FLen)) {}
503+
: TargetCodeGenInfo(std::make_unique<RISCVABIInfo>(CGT, XLen, FLen)) {
504+
SwiftInfo =
505+
std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
506+
}
504507

505508
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
506509
CodeGen::CodeGenModule &CGM) const override {

clang/test/CodeGenCXX/arm-swiftcall.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
// RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03 | FileCheck %s -check-prefixes=CHECK
22

3+
// For now just check that the RISC-V triples are accepted, but don't check the IR, as swiftcall is not yet supported.
4+
// RUN: %clang_cc1 -triple riscv32-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03
5+
// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03
6+
37
// This isn't really testing anything ARM-specific; it's just a convenient
48
// 32-bit platform.
59

0 commit comments

Comments
 (0)