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[NFC][PowerPC] Add getScalarIntVT to return MVT based on arch (llvm#115203)
Add `getScalarIntVT()` to return scalar int VT based on if arch is 32 or 64bit.
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3 files changed

+49
-57
lines changed

3 files changed

+49
-57
lines changed

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6176,7 +6176,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
61766176
SDValue GA = N->getOperand(0);
61776177
SDValue TOCbase = N->getOperand(1);
61786178

6179-
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
6179+
EVT VT = Subtarget->getScalarIntVT();
61806180
SDNode *Tmp = CurDAG->getMachineNode(
61816181
isPPC64 ? PPC::ADDIStocHA8 : PPC::ADDIStocHA, dl, VT, TOCbase, GA);
61826182

@@ -6309,7 +6309,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
63096309

63106310
SDValue ZeroReg =
63116311
CurDAG->getRegister(Subtarget->isPPC64() ? PPC::ZERO8 : PPC::ZERO,
6312-
Subtarget->isPPC64() ? MVT::i64 : MVT::i32);
6312+
Subtarget->getScalarIntVT());
63136313
unsigned LIOpcode = Subtarget->isPPC64() ? PPC::LI8 : PPC::LI;
63146314
// v16i8 LD_SPLAT addr
63156315
// ======>

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 43 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
183183
// arguments are at least 4/8 bytes aligned.
184184
bool isPPC64 = Subtarget.isPPC64();
185185
setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
186+
const MVT RegVT = Subtarget.getScalarIntVT();
186187

187188
// Set up the register classes.
188189
addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
@@ -198,7 +199,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
198199
}
199200
}
200201

201-
setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom);
202+
setOperationAction(ISD::UADDO, RegVT, Custom);
202203

203204
// Match BITREVERSE to customized fast code sequence in the td file.
204205
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
@@ -268,32 +269,24 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
268269

269270
if (isPPC64 || Subtarget.hasFPCVT()) {
270271
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
271-
AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
272-
isPPC64 ? MVT::i64 : MVT::i32);
272+
AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, RegVT);
273273
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
274-
AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
275-
isPPC64 ? MVT::i64 : MVT::i32);
274+
AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, RegVT);
276275

277276
setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
278-
AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
279-
isPPC64 ? MVT::i64 : MVT::i32);
277+
AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, RegVT);
280278
setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
281-
AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
282-
isPPC64 ? MVT::i64 : MVT::i32);
279+
AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, RegVT);
283280

284281
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
285-
AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
286-
isPPC64 ? MVT::i64 : MVT::i32);
282+
AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, RegVT);
287283
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
288-
AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
289-
isPPC64 ? MVT::i64 : MVT::i32);
284+
AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1, RegVT);
290285

291286
setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
292-
AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
293-
isPPC64 ? MVT::i64 : MVT::i32);
287+
AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, RegVT);
294288
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
295-
AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
296-
isPPC64 ? MVT::i64 : MVT::i32);
289+
AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, RegVT);
297290
} else {
298291
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
299292
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
@@ -482,9 +475,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
482475
setOperationAction(ISD::BSWAP, MVT::i64, Legal);
483476
} else {
484477
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
485-
setOperationAction(
486-
ISD::BSWAP, MVT::i64,
487-
(Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
478+
setOperationAction(ISD::BSWAP, MVT::i64,
479+
(Subtarget.hasP9Vector() && isPPC64) ? Custom : Expand);
488480
}
489481

490482
// CTPOP or CTTZ were introduced in P8/P9 respectively
@@ -709,7 +701,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
709701
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
710702
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
711703

712-
if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
704+
if (Subtarget.hasLFIWAX() || isPPC64) {
713705
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
714706
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
715707
}
@@ -3191,12 +3183,11 @@ static void setUsesTOCBasePtr(SelectionDAG &DAG) {
31913183

31923184
SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
31933185
SDValue GA) const {
3194-
const bool Is64Bit = Subtarget.isPPC64();
3195-
EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3196-
SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3197-
: Subtarget.isAIXABI()
3198-
? DAG.getRegister(PPC::R2, VT)
3199-
: DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3186+
EVT VT = Subtarget.getScalarIntVT();
3187+
SDValue Reg = Subtarget.isPPC64() ? DAG.getRegister(PPC::X2, VT)
3188+
: Subtarget.isAIXABI()
3189+
? DAG.getRegister(PPC::R2, VT)
3190+
: DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
32003191
SDValue Ops[] = { GA, Reg };
32013192
return DAG.getMemIntrinsicNode(
32023193
PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
@@ -4008,8 +3999,8 @@ SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
40083999
Entry.Node = Trmp; Args.push_back(Entry);
40094000

40104001
// TrampSize == (isPPC64 ? 48 : 40);
4011-
Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
4012-
isPPC64 ? MVT::i64 : MVT::i32);
4002+
Entry.Node =
4003+
DAG.getConstant(isPPC64 ? 48 : 40, dl, Subtarget.getScalarIntVT());
40134004
Args.push_back(Entry);
40144005

40154006
Entry.Node = FPtr; Args.push_back(Entry);
@@ -5237,13 +5228,12 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
52375228
MachineFunction &MF = DAG.getMachineFunction();
52385229
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
52395230
const PPCFrameLowering *FL = Subtarget.getFrameLowering();
5240-
bool isPPC64 = Subtarget.isPPC64();
5241-
int SlotSize = isPPC64 ? 8 : 4;
5231+
int SlotSize = Subtarget.isPPC64() ? 8 : 4;
52425232
int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
52435233
int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
52445234
NewRetAddrLoc, true);
5245-
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5246-
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
5235+
SDValue NewRetAddrFrIdx =
5236+
DAG.getFrameIndex(NewRetAddr, Subtarget.getScalarIntVT());
52475237
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
52485238
MachinePointerInfo::getFixedStack(MF, NewRetAddr));
52495239
}
@@ -5252,14 +5242,14 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
52525242

52535243
/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
52545244
/// the position of the argument.
5255-
static void
5256-
CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5257-
SDValue Arg, int SPDiff, unsigned ArgOffset,
5258-
SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
5245+
static void CalculateTailCallArgDest(
5246+
SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64, SDValue Arg,
5247+
int SPDiff, unsigned ArgOffset,
5248+
SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
52595249
int Offset = ArgOffset + SPDiff;
52605250
uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
52615251
int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
5262-
EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5252+
EVT VT = IsPPC64 ? MVT::i64 : MVT::i32;
52635253
SDValue FIN = DAG.getFrameIndex(FI, VT);
52645254
TailCallArgumentInfo Info;
52655255
Info.Arg = Arg;
@@ -5276,9 +5266,9 @@ SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
52765266
SDValue &FPOpOut, const SDLoc &dl) const {
52775267
if (SPDiff) {
52785268
// Load the LR and FP stack slot for later adjusting.
5279-
EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
52805269
LROpOut = getReturnAddrFrameIndex(DAG);
5281-
LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5270+
LROpOut = DAG.getLoad(Subtarget.getScalarIntVT(), dl, Chain, LROpOut,
5271+
MachinePointerInfo());
52825272
Chain = SDValue(LROpOut.getNode(), 1);
52835273
}
52845274
return Chain;
@@ -5320,8 +5310,9 @@ static void LowerMemOpCallTo(
53205310
MemOpChains.push_back(
53215311
DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
53225312
// Calculate and remember argument location.
5323-
} else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5324-
TailCallArguments);
5313+
} else
5314+
CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5315+
TailCallArguments);
53255316
}
53265317

53275318
static void
@@ -5672,7 +5663,7 @@ static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
56725663
const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
56735664
const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
56745665

5675-
const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5666+
const MVT RegVT = Subtarget.getScalarIntVT();
56765667
const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
56775668

56785669
// One load for the functions entry point address.
@@ -5724,7 +5715,7 @@ buildCallOperands(SmallVectorImpl<SDValue> &Ops,
57245715
const PPCSubtarget &Subtarget) {
57255716
const bool IsPPC64 = Subtarget.isPPC64();
57265717
// MVT for a general purpose register.
5727-
const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5718+
const MVT RegVT = Subtarget.getScalarIntVT();
57285719

57295720
// First operand is always the chain.
57305721
Ops.push_back(Chain);
@@ -6867,7 +6858,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
68676858
const unsigned PtrSize = IsPPC64 ? 8 : 4;
68686859
const Align PtrAlign(PtrSize);
68696860
const Align StackAlign(16);
6870-
const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
6861+
const MVT RegVT = Subtarget.getScalarIntVT();
68716862

68726863
if (ValVT == MVT::f128)
68736864
report_fatal_error("f128 is unimplemented on AIX.");
@@ -7818,7 +7809,7 @@ SDValue PPCTargetLowering::LowerCall_AIX(
78187809
assert(!CFlags.IsTailCall && "Indirect tail-calls not supported.");
78197810
const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister();
78207811
const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
7821-
const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
7812+
const MVT PtrVT = Subtarget.getScalarIntVT();
78227813
const unsigned TOCSaveOffset =
78237814
Subtarget.getFrameLowering()->getTOCSaveOffset();
78247815

@@ -8383,7 +8374,7 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
83838374
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
83848375
}
83858376
if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector())
8386-
DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
8377+
DestTy = Subtarget.getScalarIntVT();
83878378
unsigned Opc = ISD::DELETED_NODE;
83888379
switch (DestTy.SimpleTy) {
83898380
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
@@ -11319,11 +11310,11 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1131911310
Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val);
1132011311
}
1132111312
unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE;
11322-
EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
1132311313
return SDValue(
11324-
DAG.getMachineNode(Opcode, DL, MVT::Other,
11325-
DAG.getNode(ISD::ANY_EXTEND, DL, FTy, Val),
11326-
Op.getOperand(0)),
11314+
DAG.getMachineNode(
11315+
Opcode, DL, MVT::Other,
11316+
DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getScalarIntVT(), Val),
11317+
Op.getOperand(0)),
1132711318
0);
1132811319
}
1132911320
default:
@@ -17361,7 +17352,6 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
1736117352
// the stack.
1736217353
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1736317354
FuncInfo->setLRStoreRequired();
17364-
bool isPPC64 = Subtarget.isPPC64();
1736517355
auto PtrVT = getPointerTy(MF.getDataLayout());
1736617356

1736717357
if (Depth > 0) {
@@ -17373,7 +17363,7 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
1737317363
LowerFRAMEADDR(Op, DAG), MachinePointerInfo());
1737417364
SDValue Offset =
1737517365
DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
17376-
isPPC64 ? MVT::i64 : MVT::i32);
17366+
Subtarget.getScalarIntVT());
1737717367
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1737817368
DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1737917369
MachinePointerInfo());

‎llvm/lib/Target/PowerPC/PPCSubtarget.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -216,8 +216,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
216216
bool isSVR4ABI() const { return !isAIXABI(); }
217217
bool isELFv2ABI() const;
218218

219-
bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
220-
bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
219+
bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
220+
bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
221221
bool isUsingPCRelativeCalls() const;
222222

223223
/// Originally, this function return hasISEL(). Now we always enable it,
@@ -246,6 +246,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
246246
/// True if the GV will be accessed via an indirect symbol.
247247
bool isGVIndirectSymbol(const GlobalValue *GV) const;
248248

249+
MVT getScalarIntVT() const { return isPPC64() ? MVT::i64 : MVT::i32; }
250+
249251
/// Calculates the effective code model for argument GV.
250252
CodeModel::Model getCodeModel(const TargetMachine &TM,
251253
const GlobalValue *GV) const;

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