[AMDGPU] Define new feature HasFlatScratchSVSMode. NFC.

This is by analogy with HasFlatScratchSTMode and is slightly more
informative than using isGFX940Plus.

Differential Revision: https://reviews.llvm.org/D121804

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPU.td

@@ -1396,6 +1396,8 @@ def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
 
 def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
   AssemblerPredicate<(any_of FeatureGFX10_3Insts, FeatureGFX940Insts)>;
+def HasFlatScratchSVSMode : Predicate<"Subtarget->hasFlatScratchSVSMode()">,
+  AssemblerPredicate<(any_of FeatureGFX940Insts)>;
 
 def HasGFX10_AEncoding : Predicate<"Subtarget->hasGFX10_AEncoding()">,
   AssemblerPredicate<(all_of FeatureGFX10_AEncoding)>;

llvm/lib/Target/AMDGPU/FLATInstructions.td

@@ -366,7 +366,7 @@ multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit H
     def _SADDR : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1>,
                  FlatScratchInst<opName, "SS">;
 
-    let SubtargetPredicate = isGFX940Plus in
+    let SubtargetPredicate = HasFlatScratchSVSMode in
     def _SVS : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1, 1>,
                FlatScratchInst<opName, "SVS">;
 
@@ -383,7 +383,7 @@ multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
     def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>,
                  FlatScratchInst<opName, "SS">;
 
-    let SubtargetPredicate = isGFX940Plus in
+    let SubtargetPredicate = HasFlatScratchSVSMode in
     def _SVS : FLAT_Scratch_Store_Pseudo<opName, regClass, 1, 1>,
                FlatScratchInst<opName, "SVS">;
 
@@ -1272,7 +1272,7 @@ multiclass ScratchFLATLoadPats<FLAT_Pseudo inst, SDPatternOperator node, ValueTy
   }
 
   def : ScratchLoadSVaddrPat<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
-    let SubtargetPredicate = isGFX940Plus;
+    let SubtargetPredicate = HasFlatScratchSVSMode;
     let AddedComplexity = 27;
   }
 }
@@ -1288,7 +1288,7 @@ multiclass ScratchFLATStorePats<FLAT_Pseudo inst, SDPatternOperator node,
   }
 
   def : ScratchStoreSVaddrPat<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
-    let SubtargetPredicate = isGFX940Plus;
+    let SubtargetPredicate = HasFlatScratchSVSMode;
     let AddedComplexity = 27;
   }
 }
@@ -1303,7 +1303,7 @@ multiclass ScratchFLATLoadPats_D16<FLAT_Pseudo inst, SDPatternOperator node, Val
   }
 
   def : ScratchLoadSVaddrPat_D16 <!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> {
-    let SubtargetPredicate = isGFX940Plus;
+    let SubtargetPredicate = HasFlatScratchSVSMode;
     let AddedComplexity = 27;
   }
 }

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -571,6 +571,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
     return hasFlatScratchInsts() && (hasGFX10_3Insts() || hasGFX940Insts());
   }
 
+  bool hasFlatScratchSVSMode() const { return GFX940Insts; }
+
   bool hasScalarFlatScratchInsts() const {
     return ScalarFlatScratchInsts;
   }