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swift-ciswift-ci
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Merge pull request #5023 from adrian-prantl/28467349
2 parents 894be37 + 7c763e6 commit 07b196d

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3 files changed

+72
-15
lines changed

3 files changed

+72
-15
lines changed

‎lib/IRGen/IRGenSIL.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -320,8 +320,7 @@ class IRGenSILFunction :
320320
/// Keeps track of the mapping of source variables to -O0 shadow copy allocas.
321321
llvm::SmallDenseMap<StackSlotKey, Address, 8> ShadowStackSlots;
322322
llvm::SmallDenseMap<Decl *, SmallString<4>, 8> AnonymousVariables;
323-
llvm::SmallVector<std::pair<DominancePoint, llvm::Instruction *>, 8>
324-
ValueVariables;
323+
llvm::SmallDenseMap<llvm::Instruction *, DominancePoint, 8> ValueVariables;
325324
unsigned NumAnonVars = 0;
326325
unsigned NumCondFails = 0;
327326

@@ -562,9 +561,9 @@ class IRGenSILFunction :
562561
void emitDebugVariableRangeExtension(const SILBasicBlock *CurBB) {
563562
if (IGM.IRGen.Opts.Optimize)
564563
return;
565-
for (auto &Variable : reversed(ValueVariables)) {
566-
auto VarDominancePoint = Variable.first;
567-
llvm::Value *Storage = Variable.second;
564+
for (auto &Variable : ValueVariables) {
565+
auto VarDominancePoint = Variable.second;
566+
llvm::Value *Storage = Variable.first;
568567
if (getActiveDominancePoint() == VarDominancePoint ||
569568
isActiveDominancePointDominatedBy(VarDominancePoint)) {
570569
llvm::Type *ArgTys;
@@ -595,13 +594,14 @@ class IRGenSILFunction :
595594
// that this shouldn't be necessary. LiveDebugValues should be doing
596595
// this but can't in general because it currently only tracks register
597596
// locations.
598-
auto It = llvm::BasicBlock::iterator(Variable.second);
599-
auto *BB = Variable.second->getParent();
597+
llvm::Instruction *Value = Variable.first;
598+
auto It = llvm::BasicBlock::iterator(Value);
599+
auto *BB = Value->getParent();
600600
auto *CurBB = Builder.GetInsertBlock();
601601
if (BB != CurBB)
602602
for (auto I = std::next(It), E = BB->end(); I != E; ++I) {
603603
auto *DVI = dyn_cast<llvm::DbgValueInst>(I);
604-
if (DVI && DVI->getValue() == Variable.second)
604+
if (DVI && DVI->getValue() == Value)
605605
IGM.DebugInfo->getBuilder().insertDbgValueIntrinsic(
606606
DVI->getValue(), 0, DVI->getVariable(), DVI->getExpression(),
607607
DVI->getDebugLoc(), &*CurBB->getFirstInsertionPt());
@@ -649,7 +649,7 @@ class IRGenSILFunction :
649649
if (!needsShadowCopy(Storage)) {
650650
// Mark for debug value range extension unless this is a constant.
651651
if (auto *Value = dyn_cast<llvm::Instruction>(Storage))
652-
ValueVariables.push_back({getActiveDominancePoint(), Value});
652+
ValueVariables.insert({Value, getActiveDominancePoint()});
653653
return Storage;
654654
}
655655

‎test/DebugInfo/liverange-extension.swift

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,14 @@ public func rangeExtension(_ b: Bool) {
1414
// CHECK: llvm.dbg.value(metadata i32 [[I]], i64 0, metadata
1515
// CHECK: llvm.dbg.value(metadata i32 [[J:.*]], i64 0, metadata
1616
use(j)
17-
// CHECK: {{(asm sideeffect "", "r".*)|(zext i32)}} [[J]]
18-
// CHECK: asm sideeffect "", "r"
17+
// CHECK-DAG: {{(asm sideeffect "", "r".*)|(zext i32)}} [[J]]
18+
// CHECK-DAG: asm sideeffect "", "r"
1919
}
2020
let z = getInt32()
2121
use(z)
22-
// CHECK: llvm.dbg.value(metadata i32 [[I]], i64 0, metadata
2322
// CHECK-NOT: llvm.dbg.value(metadata i32 [[J]], i64 0, metadata
24-
// CHECK: llvm.dbg.value(metadata i32 [[Z:.*]], i64 0, metadata
25-
// CHECK: asm sideeffect "", "r"
26-
// CHECK: {{(asm sideeffect "", "r".*)|(zext i32)}} [[I]]
23+
// CHECK-DAG: llvm.dbg.value(metadata i32 [[I]], i64 0, metadata
24+
// CHECK-DAG: llvm.dbg.value(metadata i32 [[Z:.*]], i64 0, metadata
25+
// CHECK-DAG: {{(asm sideeffect "", "r".*)|(zext i32)}} [[I]]
26+
// CHECK-DAG: asm sideeffect "", "r"
2727
}

‎test/DebugInfo/patternvars.swift

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
// RUN: %target-swift-frontend %s -emit-ir -g -o - | %FileCheck %s
2+
3+
@_fixed_layout
4+
public struct UnicodeScalar {
5+
var _value: UInt32
6+
public var value: UInt32 { return _value }
7+
}
8+
9+
public func mangle(s: [UnicodeScalar]) -> [UnicodeScalar] {
10+
let replacementUnichar = UnicodeScalar(_value: 0)
11+
var mangledUnichars: [UnicodeScalar] = s.map {
12+
switch $0.value {
13+
case
14+
// A-Z
15+
0x0041...0x005A,
16+
// a-z
17+
0x0061...0x007A,
18+
// 0-9
19+
0x0030...0x0039,
20+
// _
21+
0x005F,
22+
// Latin (1)
23+
0x00AA...0x00AA:
24+
return $0
25+
default:
26+
return replacementUnichar
27+
}
28+
}
29+
return mangledUnichars
30+
}
31+
32+
// The patterns in the first case statement each define an anonymous variable,
33+
// which shares the storage with the expression in the switch statement. Make
34+
// sure we only emit live range extensions for the storage once per basic block.
35+
36+
// CHECK: define {{.*}}@_TFF11patternvars6mangleFT1sGSaVS_13UnicodeScalar__GSaS0__U_FS0_S0_
37+
// CHECK: call void asm sideeffect "", "r"
38+
// CHECK-NOT: call void asm sideeffect "", "r"
39+
// CHECK: br {{.*}}label
40+
// CHECK: call void asm sideeffect "", "r"
41+
// CHECK-NOT: call void asm sideeffect "", "r"
42+
// CHECK: br {{.*}}label
43+
// CHECK: call void asm sideeffect "", "r"
44+
// CHECK-NOT: call void asm sideeffect "", "r"
45+
// CHECK: br {{.*}}label
46+
// CHECK: call void asm sideeffect "", "r"
47+
// CHECK-NOT: call void asm sideeffect "", "r"
48+
// CHECK: br {{.*}}label
49+
// CHECK: call void asm sideeffect "", "r"
50+
// CHECK-NOT: call void asm sideeffect "", "r"
51+
// CHECK: br {{.*}}label
52+
// CHECK: call void asm sideeffect "", "r"
53+
// CHECK-NOT: call void asm sideeffect "", "r"
54+
// CHECK: br {{.*}}label
55+
// CHECK: call void asm sideeffect "", "r"
56+
// CHECK-NOT: call void asm sideeffect "", "r"
57+
// CHECK: br {{.*}}label

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