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Merge pull request #73461 from aschwaighofer/optional_memcpy
IRGen: memcpy instead of the outlined copy with take
2 parents f6a2793 + 62dc982 commit 1dcec50

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+28
-1
lines changed

2 files changed

+28
-1
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lib/IRGen/GenEnum.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3283,7 +3283,10 @@ namespace {
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bool zeroizeIfSensitive) const override {
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if (!ElementsAreABIAccessible) {
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emitInitializeWithTakeCall(IGF, T, dest, src);
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} else if (isOutlined || T.hasParameterizedExistential()) {
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} else if (isOutlined || T.hasParameterizedExistential() ||
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(getPayloadTypeInfo().isFixedSize() && // can use memcpy
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getPayloadTypeInfo().
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isBitwiseTakable(ResilienceExpansion::Maximal))) {
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emitIndirectInitialize(IGF, dest, src, T, IsTake, isOutlined);
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} else {
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callOutlinedCopy(IGF, dest, src, T, IsInitialization, IsTake);

test/IRGen/copy_addr_lowering.sil

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
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// RUN: %target-swift-frontend -module-name A -Xllvm -sil-disable-pass=LowerAggregateInstr -emit-ir %s | %FileCheck %s
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sil_stage lowered
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import Builtin
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import Swift
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import SwiftShims
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struct S {
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var s: ArraySlice<UInt8>
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var i: ArraySlice<UInt8>.Index
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}
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// CHECK: define{{.*}} swiftcc void @copy_test(
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// CHECK-NOT: call ptr @"$s1A1SVSgWOb"(
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// CHECK: memcpy
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// CHECK: ret void
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sil @copy_test : $@convention(thin) (@in Optional<S>) -> @out Optional<S> {
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bb0(%0 : $*Optional<S>, %1 : $*Optional<S>):
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copy_addr [take] %1 to [init] %0 : $*Optional<S>
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%5 = tuple ()
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return %5 : $()
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}

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