Merge pull request #79524 from rastogishubham/FixASANBug

When emitting an LValue of a LoadExpr during SILGen, the Expression passed as a SILLocation for the LValue was the parent LoadExpr instead of the SubExpr that contains the LValue for the load. This leads to the SILLocation to be marked as implicit, because a LoadExpr is always an implicit expression.

An implicit SILLocation is not emitted when doing IRGen as it is considered to be hidden from debug info and thus we lose the debug location for the LValue of a LoadExpr.

This patch fixes this issue and thus, preserves the location information.

Author: rastogishubham

lib/SILGen/SILGenExpr.cpp

@@ -1094,7 +1094,8 @@ RValue RValueEmitter::visitLoadExpr(LoadExpr *E, SGFContext C) {
   // We can't load at immediate +0 from the lvalue without deeper analysis,
   // since the access will be immediately ended and might invalidate the value
   // we loaded.
-  return SGF.emitLoadOfLValue(E, std::move(lv), C.withFollowingSideEffects());
+  return SGF.emitLoadOfLValue(E->getSubExpr(), std::move(lv),
+                              C.withFollowingSideEffects());
 }
 
 SILValue SILGenFunction::emitTemporaryAllocation(SILLocation loc, SILType ty,

test/DebugInfo/shadowcopy-linetable.swift

@@ -1,21 +1,35 @@
-// RUN: %target-swift-frontend %s -emit-ir -g -o - | %FileCheck %s
-
+// RUN: %target-swift-frontend %s -emit-sil -Xllvm -sil-print-debuginfo -Xllvm -sil-print-debuginfo-verbose -g -o - | %FileCheck %s --check-prefix=SILCHECK
+// RUN: %target-swift-frontend %s -emit-ir -g -o - | %FileCheck %s --check-prefix=IRCHECK
 func markUsed<T>(_ t: T) {}
 
 func foo(_ x: inout Int64) {
+
+  // Make sure that the begin_access, load, and end_access instructions
+  // are not marked as isImplicit: true. They should not be implicit
+  // because they are generated from a member_ref_expr which is the
+  // lvalue SubExpr of a LoadExpr. LoadExpr's are always implicit, but 
+  // that doesn't necessarily mean their SubExprs are implicit as well.
+  // SILCHECK: sil hidden @$s4main3fooyys5Int64VzF
+  // SILCHECK: debug_value %0, var, name "x", argno 1, expr op_deref, loc {{.*}} isImplicit: false, isAutoGenerated: false, isHiddenFromDebugInfo: false, scope 7 // id: %1
+  // SILCHECK: begin_access [read] [static] %0, loc {{.*}} isImplicit: false, isAutoGenerated: false, isHiddenFromDebugInfo: false
+  // SILCHECK-NEXT: load %2, loc {{.*}} isImplicit: false, isAutoGenerated: false, isHiddenFromDebugInfo: false
+  // SILCHECK-NEXT: end_access %2, loc * {{.*}} isImplicit: false, isAutoGenerated: true, isHiddenFromDebugInfo: true
+
   // Make sure the shadow copy is being made in the prologue or (at
   // line 0), but the code to load the value from the inout storage is
   // not.
-  // CHECK: define hidden swiftcc void @"$s4main3fooyys5Int64VzF"
-  // CHECK: %[[X:.*]] = alloca ptr, align {{(4|8)}}
-  // CHECK-NEXT: #dbg_declare
-  // CHECK-NEXT: call void @llvm.memset.{{.*}}(ptr align {{(4|8)}} %[[X]], i8 0
-  // CHECK: store ptr %0, ptr %[[X]], align {{(4|8)}}
-  // CHECK-SAME: !dbg ![[LOC0:.*]]
-  // CHECK-NEXT: getelementptr inbounds %Ts5Int64V, ptr %0, i32 0, i32 0,
-  // CHECK-SAME: !dbg ![[LOC0]]
-  // CHECK: ![[LOC0]] = !DILocation(line: 0,
-  // CHECK: !DILocation(line: [[@LINE+1]],
+  // IRCHECK: define hidden swiftcc void @"$s4main3fooyys5Int64VzF"
+  // IRCHECK: %[[X:.*]] = alloca ptr, align {{(4|8)}}
+  // IRCHECK-NEXT: #dbg_declare
+  // IRCHECK-NEXT: call void @llvm.memset.{{.*}}(ptr align {{(4|8)}} %[[X]], i8 0
+  // IRCHECK: store ptr %0, ptr %[[X]], align {{(4|8)}}
+  // IRCHECK-SAME: !dbg ![[LOC0:.*]]
+  // IRCHECK-NEXT: %[[VALUE:.*]] = getelementptr inbounds %Ts5Int64V, ptr %0, i32 0, i32 0,
+  // IRCHECK-SAME: !dbg ![[LOCLOAD:.*]]
+  // IRCHECK-NEXT: load i64, ptr %[[VALUE]], align {{(4|8)}}
+  // IRCHECK-SAME: !dbg ![[LOCLOAD]]
+  // IRCHECK: ![[LOC0]] = !DILocation(line: 0,
+  // IRCHECK: !DILocation(line: [[@LINE+1]],
   x = x + 2
 }