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Simon Moll
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[VE] Add +vpu attribute
`+vpu` controls whether VEISelLowering adds any vregs. This defaults to `-vpu` to have scalar code generation out of the box. We bring up vector isel under the `+vpu` flag. Once vector isel is stable we switch to `+vpu` and advertise vregs and vops in TTI. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D90465
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7 files changed

+70
-42
lines changed

7 files changed

+70
-42
lines changed

‎llvm/lib/Target/VE/VE.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,9 @@ include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// VE Subtarget features.
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//
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def FeatureEnableVPU
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: SubtargetFeature<"vpu", "EnableVPU", "true",
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"Enable the VPU">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions

‎llvm/lib/Target/VE/VEISelLowering.cpp

Lines changed: 47 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -57,46 +57,48 @@ void VETargetLowering::initRegisterClasses() {
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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addRegisterClass(MVT::f128, &VE::F128RegClass);
5959

60-
addRegisterClass(MVT::v2i32, &VE::V64RegClass);
61-
addRegisterClass(MVT::v4i32, &VE::V64RegClass);
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addRegisterClass(MVT::v8i32, &VE::V64RegClass);
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addRegisterClass(MVT::v16i32, &VE::V64RegClass);
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addRegisterClass(MVT::v32i32, &VE::V64RegClass);
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addRegisterClass(MVT::v64i32, &VE::V64RegClass);
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addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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addRegisterClass(MVT::v256i32, &VE::V64RegClass);
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addRegisterClass(MVT::v512i32, &VE::V64RegClass);
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addRegisterClass(MVT::v2i64, &VE::V64RegClass);
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addRegisterClass(MVT::v4i64, &VE::V64RegClass);
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addRegisterClass(MVT::v8i64, &VE::V64RegClass);
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addRegisterClass(MVT::v16i64, &VE::V64RegClass);
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addRegisterClass(MVT::v32i64, &VE::V64RegClass);
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addRegisterClass(MVT::v64i64, &VE::V64RegClass);
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addRegisterClass(MVT::v128i64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i64, &VE::V64RegClass);
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addRegisterClass(MVT::v2f32, &VE::V64RegClass);
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addRegisterClass(MVT::v4f32, &VE::V64RegClass);
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addRegisterClass(MVT::v8f32, &VE::V64RegClass);
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addRegisterClass(MVT::v16f32, &VE::V64RegClass);
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addRegisterClass(MVT::v32f32, &VE::V64RegClass);
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addRegisterClass(MVT::v64f32, &VE::V64RegClass);
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addRegisterClass(MVT::v128f32, &VE::V64RegClass);
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addRegisterClass(MVT::v256f32, &VE::V64RegClass);
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addRegisterClass(MVT::v512f32, &VE::V64RegClass);
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addRegisterClass(MVT::v2f64, &VE::V64RegClass);
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addRegisterClass(MVT::v4f64, &VE::V64RegClass);
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addRegisterClass(MVT::v8f64, &VE::V64RegClass);
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addRegisterClass(MVT::v16f64, &VE::V64RegClass);
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addRegisterClass(MVT::v32f64, &VE::V64RegClass);
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addRegisterClass(MVT::v64f64, &VE::V64RegClass);
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addRegisterClass(MVT::v128f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i1, &VE::VMRegClass);
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addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
60+
if (Subtarget->enableVPU()) {
61+
addRegisterClass(MVT::v2i32, &VE::V64RegClass);
62+
addRegisterClass(MVT::v4i32, &VE::V64RegClass);
63+
addRegisterClass(MVT::v8i32, &VE::V64RegClass);
64+
addRegisterClass(MVT::v16i32, &VE::V64RegClass);
65+
addRegisterClass(MVT::v32i32, &VE::V64RegClass);
66+
addRegisterClass(MVT::v64i32, &VE::V64RegClass);
67+
addRegisterClass(MVT::v128i32, &VE::V64RegClass);
68+
addRegisterClass(MVT::v256i32, &VE::V64RegClass);
69+
addRegisterClass(MVT::v512i32, &VE::V64RegClass);
70+
71+
addRegisterClass(MVT::v2i64, &VE::V64RegClass);
72+
addRegisterClass(MVT::v4i64, &VE::V64RegClass);
73+
addRegisterClass(MVT::v8i64, &VE::V64RegClass);
74+
addRegisterClass(MVT::v16i64, &VE::V64RegClass);
75+
addRegisterClass(MVT::v32i64, &VE::V64RegClass);
76+
addRegisterClass(MVT::v64i64, &VE::V64RegClass);
77+
addRegisterClass(MVT::v128i64, &VE::V64RegClass);
78+
addRegisterClass(MVT::v256i64, &VE::V64RegClass);
79+
80+
addRegisterClass(MVT::v2f32, &VE::V64RegClass);
81+
addRegisterClass(MVT::v4f32, &VE::V64RegClass);
82+
addRegisterClass(MVT::v8f32, &VE::V64RegClass);
83+
addRegisterClass(MVT::v16f32, &VE::V64RegClass);
84+
addRegisterClass(MVT::v32f32, &VE::V64RegClass);
85+
addRegisterClass(MVT::v64f32, &VE::V64RegClass);
86+
addRegisterClass(MVT::v128f32, &VE::V64RegClass);
87+
addRegisterClass(MVT::v256f32, &VE::V64RegClass);
88+
addRegisterClass(MVT::v512f32, &VE::V64RegClass);
89+
90+
addRegisterClass(MVT::v2f64, &VE::V64RegClass);
91+
addRegisterClass(MVT::v4f64, &VE::V64RegClass);
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addRegisterClass(MVT::v8f64, &VE::V64RegClass);
93+
addRegisterClass(MVT::v16f64, &VE::V64RegClass);
94+
addRegisterClass(MVT::v32f64, &VE::V64RegClass);
95+
addRegisterClass(MVT::v64f64, &VE::V64RegClass);
96+
addRegisterClass(MVT::v128f64, &VE::V64RegClass);
97+
addRegisterClass(MVT::v256f64, &VE::V64RegClass);
98+
99+
addRegisterClass(MVT::v256i1, &VE::VMRegClass);
100+
addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
101+
}
100102
}
101103

102104
void VETargetLowering::initSPUActions() {
@@ -262,6 +264,10 @@ void VETargetLowering::initSPUActions() {
262264
/// } Atomic isntructions
263265
}
264266

267+
void VETargetLowering::initVPUActions() {
268+
// TODO upstream vector isel
269+
}
270+
265271
SDValue
266272
VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
267273
bool IsVarArg,
@@ -842,7 +848,7 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
842848

843849
initRegisterClasses();
844850
initSPUActions();
845-
// TODO initVPUActions();
851+
initVPUActions();
846852

847853
setStackPointerRegisterToSaveRestore(VE::SX11);
848854

‎llvm/lib/Target/VE/VEISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ class VETargetLowering : public TargetLowering {
4545

4646
void initRegisterClasses();
4747
void initSPUActions();
48-
// TODO void initVPUActions();
48+
void initVPUActions();
4949

5050
public:
5151
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);

‎llvm/lib/Target/VE/VESubtarget.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,9 @@ void VESubtarget::anchor() {}
2727

2828
VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU,
2929
StringRef FS) {
30+
// Default feature settings
31+
EnableVPU = false;
32+
3033
// Determine default and user specified characteristics
3134
std::string CPUName = std::string(CPU);
3235
if (CPUName.empty())

‎llvm/lib/Target/VE/VESubtarget.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,13 @@ class VESubtarget : public VEGenSubtargetInfo {
3232
Triple TargetTriple;
3333
virtual void anchor();
3434

35+
/// Features {
36+
37+
// Emit VPU instructions
38+
bool EnableVPU;
39+
40+
/// } Features
41+
3542
VEInstrInfo InstrInfo;
3643
VETargetLowering TLInfo;
3744
SelectionDAGTargetInfo TSInfo;
@@ -55,6 +62,8 @@ class VESubtarget : public VEGenSubtargetInfo {
5562

5663
bool enableMachineScheduler() const override;
5764

65+
bool enableVPU() const { return EnableVPU; }
66+
5867
/// ParseSubtargetFeatures - Parses features string setting specified
5968
/// subtarget options. Definition of function is auto generated by tblgen.
6069
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);

‎llvm/lib/Target/VE/VETargetTransformInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,8 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
3333
const VESubtarget *getST() const { return ST; }
3434
const VETargetLowering *getTLI() const { return TLI; }
3535

36+
bool enableVPU() const { return getST()->enableVPU(); }
37+
3638
public:
3739
explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
3840
: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),

‎llvm/test/CodeGen/VE/Vector/feature_vpu.ll

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
; RUN: llc -march=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
2+
3+
; CHECK: Available features for this target:
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; CHECK: vpu - Enable the VPU.
5+

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