[send-non-sendable] When logging the pseudo-ir dump out the root representative value associated with pseudo-ir ids.

Really, we should just be using representative values here in general since it
serves the same purpose and makes it easier to trace back values. But this in
the short term makes the output easier to reason about.

Author: gottesmm

include/swift/SILOptimizer/Utils/PartitionUtils.h

@@ -141,6 +141,8 @@ class PartitionOp {
 
   PartitionOpKind getKind() const { return OpKind; }
 
+  ArrayRef<Element> getOpArgs() const { return OpArgs; }
+
   SILInstruction *getSourceInst(bool assertNonNull = false) const {
     assert(!assertNonNull ||
            sourceInst && "PartitionOps should be assigned SILInstruction"

lib/SILOptimizer/Mandatory/SendNonSendable.cpp

@@ -225,6 +225,10 @@ class PartitionOpTranslator {
   /// ensure simplifyVal is called on SILValues before entering into this map
   llvm::DenseMap<SILValue, TrackableValueState> equivalenceClassValuesToState;
 
+#ifndef NDEBUG
+  llvm::DenseMap<unsigned, SILValue> stateIndexToEquivalenceClass;
+#endif
+
   // some values that AccessStorage claims are uniquely identified are still
   // captured (e.g. in a closure). This set is initialized upon
   // PartitionOpTranslator construction to store those values.
@@ -245,9 +249,13 @@ class PartitionOpTranslator {
 
     // If we did not insert, just return the already stored value.
     if (!iter.second) {
-      return {value, iter.first->second};
+      return {iter.first->first, iter.first->second};
     }
 
+#ifndef NDEBUG
+    self->stateIndexToEquivalenceClass[iter.first->second.getID()] = value;
+#endif
+
     // Otherwise, we need to compute our true aliased and sendable values. Begi
     // by seeing if we have a value that we can prove is not aliased.
     if (isAddress(value)) {
@@ -930,6 +938,10 @@ class PartitionOpTranslator {
     //translate each SIL instruction to a PartitionOp, if necessary
     std::vector<PartitionOp> partitionOps;
     int lastTranslationIndex = -1;
+#ifndef NDEBUG
+    llvm::SmallVector<unsigned, 8> opsToPrint;
+#endif
+
     for (SILInstruction &instruction : *basicBlock) {
       auto ops = translateSILInstruction(&instruction);
       for (PartitionOp &op : ops) {
@@ -943,10 +955,32 @@ class PartitionOpTranslator {
               instruction.getLoc().getSourceLoc().printLineAndColumn(
                   llvm::dbgs(), function->getASTContext().SourceMgr);
               llvm::dbgs() << " │ translation #" << translationIndex;
-              llvm::dbgs() << "\n └─────╼ ";
-            } else { llvm::dbgs() << "      └╼ "; } op.print(llvm::dbgs());
-            lastTranslationIndex = translationIndex;);
+              llvm::dbgs() << "\n ├─────╼ ";
+            } else {
+              llvm::dbgs() << " │    └╼ ";
+            }
+            op.print(llvm::dbgs());
+            lastTranslationIndex = translationIndex;
+        );
       }
+      LLVM_DEBUG(
+          if (ops.size()) {
+            llvm::dbgs() << " └─────╼ Used Values\n";
+            SWIFT_DEFER { opsToPrint.clear(); };
+            for (PartitionOp &op : ops) {
+              // Now dump our the root value we map.
+              for (unsigned opArg : op.getOpArgs()) {
+                // If we didn't insert, skip this. We only emit this once.
+                opsToPrint.push_back(opArg);
+              }
+            }
+            sortUnique(opsToPrint);
+            for (unsigned opArg : opsToPrint) {
+              llvm::dbgs() << "          └╼ ";
+              llvm::dbgs() << "%%" << opArg << ": " << stateIndexToEquivalenceClass[opArg];
+            }
+          }
+       );
     }
 
     return partitionOps;