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Address review comments
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lib/SILOptimizer/Mandatory/Differentiation.cpp

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -483,22 +483,16 @@ SILFunction *DifferentiationTransformer::getUnwrappedCurryThunkFunction(
483483
if (autoCE == nullptr)
484484
return nullptr;
485485

486-
AbstractFunctionDecl *afd = nullptr;
487-
Expr *expr = autoCE->getUnwrappedCurryThunkExpr();
488-
switch (autoCE->getThunkKind()) {
489-
default:
490-
llvm_unreachable("Only single and double curry thunks are expected");
491-
case AutoClosureExpr::Kind::SingleCurryThunk:
492-
case AutoClosureExpr::Kind::DoubleCurryThunk:
493-
afd = cast<AbstractFunctionDecl>(cast<ApplyExpr>(expr)->getCalledValue(
494-
/*skipFunctionConversions=*/true));
495-
break;
496-
}
497-
assert(afd);
486+
auto *ae = dyn_cast_or_null<ApplyExpr>(autoCE->getUnwrappedCurryThunkExpr());
487+
if (ae == nullptr)
488+
return nullptr;
498489

490+
AbstractFunctionDecl *afd = cast<AbstractFunctionDecl>(ae->getCalledValue(
491+
/*skipFunctionConversions=*/true));
499492
auto silFnIt = afdToSILFn.find(afd);
500493
if (silFnIt == afdToSILFn.end()) {
501-
assert(afdToSILFn.empty());
494+
assert(afdToSILFn.empty() && "Expect all 'afdToSILFn' cache entries to be "
495+
"filled at once on the first access attempt");
502496

503497
SILModule *module = getTransform().getModule();
504498
for (SILFunction &currentFunc : module->getFunctions()) {
@@ -518,13 +512,16 @@ SILFunction *DifferentiationTransformer::getUnwrappedCurryThunkFunction(
518512
if (currentAFD->hasCurriedSelf()) {
519513
auto [_, wasEmplace] =
520514
afdToSILFn.try_emplace(currentAFD, &currentFunc);
521-
assert(wasEmplace);
515+
assert(wasEmplace && "Expect all 'afdToSILFn' cache entries to be "
516+
"filled at once on the first access attempt");
522517
}
523518
}
524519
}
525520

526521
silFnIt = afdToSILFn.find(afd);
527-
assert(silFnIt != afdToSILFn.end());
522+
assert(silFnIt != afdToSILFn.end() &&
523+
"Expect present curry thunk to SIL function mapping after "
524+
"'afdToSILFn' cache fill");
528525
}
529526

530527
return silFnIt->second;

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