X86: bump the minimum required CPU to IvyBridge

Bump the minimum supported CPU to IvyBridge so that we can take
advantage of the F16C/CVT16 extensions to support half floating point
rounding.  This avoids the undefined reference to `__extendsfhf2` in the
FP16 support.

Author: compnerd

lib/ClangImporter/ClangImporter.cpp

@@ -780,6 +780,16 @@ importer::addCommonInvocationArguments(
     invocationArgStrs.push_back("-mcx16");
   }
 
+  if (triple.isX86()) {
+    // Enable the FC16/CVT16 extensions which provide half prevision floating
+    // point support on x86_64.  This bumps the minimum requirement of the CPU
+    // to Ivy Bridge, however, Windows 10 (at least as of 1709) requires
+    // ~Broadwell.  At this point, the complexity of supporting an older release
+    // no longer is justified.  For uniformity, bump the minimum x86 CPU on all
+    // the targets.
+    invocationArgStrs.push_back("-mf16c");
+  }
+
   if (!importerOpts.Optimization.empty()) {
     invocationArgStrs.push_back(importerOpts.Optimization);
   }

stdlib/cmake/modules/AddSwiftStdlib.cmake

@@ -288,6 +288,18 @@ function(_add_target_variant_c_compile_flags)
     endif()
   endif()
 
+  # Avoid the need for the FP16 truncation and extension routines from
+  # compiler-rt by assuming that we have hardware capable of performing
+  # half-precision floating point conversions.  This effectively pins the
+  # minimum CPU requirements to Ivy Bridge (~2013).
+  if(CFLAGS_ARCH STREQUAL x86_64 OR CFLAGS_ARCH STREQUAL i686)
+    if(SWIFT_COMPILER_IS_MSVC_LIKE)
+      list(APPEND result /clang:-mf16c)
+    else()
+      list(APPEND result -mf16c)
+    endif()
+  endif()
+
   if(CFLAGS_ENABLE_ASSERTIONS)
     list(APPEND result "-UNDEBUG")
   else()

stdlib/public/runtime/Float16Support.cpp

@@ -15,6 +15,7 @@
 // __gnu_h2f_ieee
 // __gnu_f2h_ieee
 // __truncdfhf2
+// __extendhfxf2
 //
 // On Darwin platforms, these are provided by the host compiler-rt, but we
 // can't depend on that everywhere, so we have to provide them in the Swift
@@ -30,7 +31,7 @@
 // Android NDK <r21 do not provide `__aeabi_d2h` in the compiler runtime,
 // provide shims in that case.
 #if (defined(__ANDROID__) && defined(__ARM_ARCH_7A__) && defined(__ARM_EABI__)) || \
-  ((defined(__i386__) || defined(__i686__) || defined(__x86_64__)) && !defined(__APPLE__) && !defined(__linux__))
+    (!defined(__APPLE__) && (defined(__i386__) || defined(__x86_64__)))
 
 #include "swift/shims/Visibility.h"
 
@@ -150,10 +151,23 @@ SWIFT_RUNTIME_EXPORT unsigned short __truncdfhf2(double d) {
   return __gnu_f2h_ieee(f);
 }
 
+// F16C does not cover FP80 conversions, so we still need an implementation
+// here.
+#if (defined(__i386__) || defined(__x86_64__)) &&                               \
+    !(defined(__ANDROID__) || defined(__APPLE__) || defined(_WIN32))
+
+SWIFT_RUNTIME_EXPORT long double __extendhfxf2(_Float16 h) {
+  __builtin_trap();
+}
+
+#endif // (defined(__i386__) || defined(__x86_64__)) &&
+       // !(defined(__ANDROID__) || defined(__APPLE__) || defined(_WIN32))
+
 #if defined(__ARM_EABI__)
 SWIFT_RUNTIME_EXPORT unsigned short __aeabi_d2h(double d) {
   return __truncdfhf2(d);
 }
 #endif
 
-#endif // defined(__x86_64__) && !defined(__APPLE__)
+#endif // (defined(__ANDROID__) && defined(__ARM_ARCH_7A__) && defined(__ARM_EABI__)) ||
+       // (!defined(__APPLE__) && (defined(__i386__) || defined(__x86_64__)))

test/IRGen/ordering_x86.sil

@@ -41,4 +41,4 @@ bb0:
 // the order of features differs.
 
 // X86_64: define{{( protected)?}} swiftcc void @baz{{.*}}#0
-// X86_64: #0 = {{.*}}"target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+ssse3,+x87"
+// X86_64: #0 = {{.*}}"target-features"="+avx,+crc32,+cx16,+cx8,+f16c,+fxsr,+mmx,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"