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LargeTypesReg2Mem: Fix copy_addr optimization
Make sure that the value we store is the loaded value ... rdar://123340151
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2 files changed

+22
-1
lines changed

2 files changed

+22
-1
lines changed

lib/IRGen/LoadableByAddress.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3306,7 +3306,7 @@ bool Peepholes::optimizeLoad(SILBasicBlock &BB, SILInstruction *I) {
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if (next2It == BB.end())
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return false;
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auto *store = dyn_cast<StoreInst>(&*next2It);
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if (!store)
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if (!store || store->getSrc() != LI)
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return false;
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if (ignore(store))
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return false;

test/IRGen/loadable_by_address_reg2mem.sil

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,16 @@ struct Y {
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var y2: X
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}
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class C1 {
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}
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sil_vtable C1 {
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}
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struct Small {
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var x1 : Int
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}
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// CHECK: sil @test1 : $@convention(thin) () -> () {
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// CHECK: bb0:
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// CHECK: %0 = alloc_stack $Optional<X>
@@ -248,3 +258,14 @@ bb0:
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%t = tuple ()
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return %t : $()
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}
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sil @test10 : $@convention(thin) (@in_guaranteed C1, @in Small) -> () {
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bb0(%0 : $*C1, %1 : $*Small):
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%2 = load %1 : $*Small
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%3 = load %0 : $*C1
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retain_value %3 : $C1
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store %2 to %1 : $*Small
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retain_value %3 : $C1
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%t = tuple ()
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return %t : $()
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}

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