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Merge pull request #18807 from eeckstein/fix-non-determinism
2 parents f779d5e + fc44ec8 commit eafbf43

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5 files changed

+12
-3
lines changed

5 files changed

+12
-3
lines changed

lib/SILOptimizer/Transforms/SILMem2Reg.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ typedef llvm::DenseMap<DomTreeNode *, unsigned> DomTreeLevelMap;
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/// Promotes a single AllocStackInst into registers..
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class StackAllocationPromoter {
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typedef llvm::DenseSet<SILBasicBlock *> BlockSet;
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typedef llvm::SmallSetVector<SILBasicBlock *, 16> BlockSet;
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typedef llvm::DenseMap<SILBasicBlock *, SILInstruction *> BlockToInstMap;
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// Use a priority queue keyed on dominator tree level so that inserted nodes
@@ -794,7 +794,7 @@ void StackAllocationPromoter::promoteAllocationToPhi() {
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// The successor node is a new PHINode. If this is a new PHI node
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// then it may require additional definitions, so add it to the PQ.
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if (PhiBlocks.insert(Succ).second)
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if (PhiBlocks.insert(Succ))
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PQ.push(std::make_pair(SuccNode, SuccLevel));
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}
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lib/SILOptimizer/Transforms/SimplifyCFG.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2530,7 +2530,9 @@ static void removeArgument(SILBasicBlock *BB, unsigned i) {
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// Determine the set of predecessors in case any predecessor has
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// two edges to this block (e.g. a conditional branch where both
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// sides reach this block).
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llvm::SmallPtrSet<SILBasicBlock *, 4> PredBBs;
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llvm::SetVector<SILBasicBlock *,SmallVector<SILBasicBlock *, 8>,
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SmallPtrSet<SILBasicBlock *, 8>> PredBBs;
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for (auto *Pred : BB->getPredecessorBlocks())
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PredBBs.insert(Pred);
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tools/SourceKit/tools/swift-lang/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ add_swift_library(swiftSwiftLang SHARED
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UIDs.swift.gyb
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DEPENDS ${DEPENDS_LIST}
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SWIFT_MODULE_DEPENDS_OSX Darwin
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PRIVATE_LINK_LIBRARIES ${SOURCEKITD_LINK_LIBS}
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SWIFT_COMPILE_FLAGS ${EXTRA_COMPILE_FLAGS}
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INSTALL_IN_COMPONENT ${INSTALLED_COMP}

utils/build-presets.ini

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,7 @@ dash-dash
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skip-test-ios-host
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skip-test-tvos-host
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skip-test-watchos-host
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check-incremental-compilation
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[preset: buildbot,tools=RA,stdlib=RDA]

utils/check-incremental

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Original file line numberDiff line numberDiff line change
@@ -74,6 +74,11 @@ def main():
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if VERBOSE:
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print("Reference compilation of " + output_file + ":")
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# As a workaround for rdar://problem/43442957 and rdar://problem/43439465
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# we have to "warm-up" the clang module cache. Without that in some cases
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# we end up with small differences in the debug info.
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compile_and_stat(new_args, output_file)
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reference_md5, reference_time = compile_and_stat(new_args, output_file)
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subprocess.check_call(["cp", output_file, output_file + ".ref.o"])

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