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thurstondthurstond
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Address Vitaly's feedback - split into base change
1 parent 9585fd7 commit 32b6431

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7 files changed

+156
-180
lines changed

7 files changed

+156
-180
lines changed

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Lines changed: 100 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -2624,8 +2624,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
26242624

26252625
FixedVectorType *ParamType =
26262626
cast<FixedVectorType>(I.getArgOperand(0)->getType());
2627-
if (I.arg_size() == 2)
2628-
assert(I.getArgOperand(0)->getType() == I.getArgOperand(1)->getType());
2627+
assert(I.arg_size() != 2 || I.getArgOperand(0)->getType() == I.getArgOperand(1)->getType());
26292628

26302629
[[maybe_unused]] FixedVectorType *ReturnType =
26312630
cast<FixedVectorType>(I.getType());
@@ -4189,6 +4188,87 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
41894188
setOriginForNaryOp(I);
41904189
}
41914190

4191+
void handleAVXHorizontalAddSubIntrinsic(IntrinsicInst &I) {
4192+
// Approximation only:
4193+
// output = horizontal_add/sub(A, B)
4194+
// => shadow[output] = horizontal_add(shadow[A], shadow[B])
4195+
//
4196+
// We always use horizontal add instead of subtract, because subtracting
4197+
// a fully uninitialized shadow would result in a fully initialized shadow.
4198+
//
4199+
// - If we add two adjacent zero (initialized) shadow values, the
4200+
// result always be zero i.e., no false positives.
4201+
// - If we add two shadows, one of which is uninitialized, the
4202+
// result will always be non-zero i.e., no false negatives.
4203+
// - However, we can have false negatives if we do an addition that wraps
4204+
// to zero; we consider this an acceptable tradeoff for performance.
4205+
//
4206+
// To make shadow propagation precise, we want the equivalent of
4207+
// "horizontal OR", but this is not available for SSE3/SSSE3/AVX/AVX2.
4208+
4209+
Intrinsic::ID shadowIntrinsicID = I.getIntrinsicID();
4210+
4211+
switch (I.getIntrinsicID()) {
4212+
case Intrinsic::x86_sse3_hsub_ps:
4213+
shadowIntrinsicID = Intrinsic::x86_sse3_hadd_ps;
4214+
break;
4215+
4216+
case Intrinsic::x86_sse3_hsub_pd:
4217+
shadowIntrinsicID = Intrinsic::x86_sse3_hadd_pd;
4218+
break;
4219+
4220+
case Intrinsic::x86_ssse3_phsub_d:
4221+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_d;
4222+
break;
4223+
4224+
case Intrinsic::x86_ssse3_phsub_d_128:
4225+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_d_128;
4226+
break;
4227+
4228+
case Intrinsic::x86_ssse3_phsub_w:
4229+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_w;
4230+
break;
4231+
4232+
case Intrinsic::x86_ssse3_phsub_w_128:
4233+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_w_128;
4234+
break;
4235+
4236+
case Intrinsic::x86_ssse3_phsub_sw:
4237+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_sw;
4238+
break;
4239+
4240+
case Intrinsic::x86_ssse3_phsub_sw_128:
4241+
shadowIntrinsicID = Intrinsic::x86_ssse3_phadd_sw_128;
4242+
break;
4243+
4244+
case Intrinsic::x86_avx_hsub_pd_256:
4245+
shadowIntrinsicID = Intrinsic::x86_avx_hadd_pd_256;
4246+
break;
4247+
4248+
case Intrinsic::x86_avx_hsub_ps_256:
4249+
shadowIntrinsicID = Intrinsic::x86_avx_hadd_ps_256;
4250+
break;
4251+
4252+
case Intrinsic::x86_avx2_phsub_d:
4253+
shadowIntrinsicID = Intrinsic::x86_avx2_phadd_d;
4254+
break;
4255+
4256+
case Intrinsic::x86_avx2_phsub_w:
4257+
shadowIntrinsicID = Intrinsic::x86_avx2_phadd_w;
4258+
break;
4259+
4260+
case Intrinsic::x86_avx2_phsub_sw:
4261+
shadowIntrinsicID = Intrinsic::x86_avx2_phadd_sw;
4262+
break;
4263+
4264+
default:
4265+
break;
4266+
}
4267+
4268+
return handleIntrinsicByApplyingToShadow(I, shadowIntrinsicID,
4269+
/*trailingVerbatimArgs*/ 0);
4270+
}
4271+
41924272
/// Handle Arm NEON vector store intrinsics (vst{2,3,4}, vst1x_{2,3,4},
41934273
/// and vst{2,3,4}lane).
41944274
///
@@ -4735,49 +4815,33 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
47354815
handleVtestIntrinsic(I);
47364816
break;
47374817

4738-
// Packed Horizontal Add/Subtract
4739-
case Intrinsic::x86_ssse3_phadd_w:
4740-
case Intrinsic::x86_ssse3_phadd_w_128:
4741-
case Intrinsic::x86_avx2_phadd_w:
4742-
case Intrinsic::x86_ssse3_phsub_w:
4743-
case Intrinsic::x86_ssse3_phsub_w_128:
4744-
case Intrinsic::x86_avx2_phsub_w: {
4745-
handlePairwiseShadowOrIntrinsic(I, /*ReinterpretElemWidth=*/16);
4746-
break;
4747-
}
4748-
4749-
// Packed Horizontal Add/Subtract
4818+
case Intrinsic::x86_sse3_hadd_ps:
4819+
case Intrinsic::x86_sse3_hadd_pd:
47504820
case Intrinsic::x86_ssse3_phadd_d:
47514821
case Intrinsic::x86_ssse3_phadd_d_128:
4752-
case Intrinsic::x86_avx2_phadd_d:
4753-
case Intrinsic::x86_ssse3_phsub_d:
4754-
case Intrinsic::x86_ssse3_phsub_d_128:
4755-
case Intrinsic::x86_avx2_phsub_d: {
4756-
handlePairwiseShadowOrIntrinsic(I, /*ReinterpretElemWidth=*/32);
4757-
break;
4758-
}
4759-
4760-
// Packed Horizontal Add/Subtract and Saturate
4822+
case Intrinsic::x86_ssse3_phadd_w:
4823+
case Intrinsic::x86_ssse3_phadd_w_128:
47614824
case Intrinsic::x86_ssse3_phadd_sw:
47624825
case Intrinsic::x86_ssse3_phadd_sw_128:
4763-
case Intrinsic::x86_avx2_phadd_sw:
4764-
case Intrinsic::x86_ssse3_phsub_sw:
4765-
case Intrinsic::x86_ssse3_phsub_sw_128:
4766-
case Intrinsic::x86_avx2_phsub_sw: {
4767-
handlePairwiseShadowOrIntrinsic(I, /*ReinterpretElemWidth=*/16);
4768-
break;
4769-
}
4770-
4771-
// Packed Single/Double Precision Floating-Point Horizontal Add
4772-
case Intrinsic::x86_sse3_hadd_ps:
4773-
case Intrinsic::x86_sse3_hadd_pd:
47744826
case Intrinsic::x86_avx_hadd_pd_256:
47754827
case Intrinsic::x86_avx_hadd_ps_256:
4828+
case Intrinsic::x86_avx2_phadd_d:
4829+
case Intrinsic::x86_avx2_phadd_w:
4830+
case Intrinsic::x86_avx2_phadd_sw:
47764831
case Intrinsic::x86_sse3_hsub_ps:
47774832
case Intrinsic::x86_sse3_hsub_pd:
4833+
case Intrinsic::x86_ssse3_phsub_d:
4834+
case Intrinsic::x86_ssse3_phsub_d_128:
4835+
case Intrinsic::x86_ssse3_phsub_w:
4836+
case Intrinsic::x86_ssse3_phsub_w_128:
4837+
case Intrinsic::x86_ssse3_phsub_sw:
4838+
case Intrinsic::x86_ssse3_phsub_sw_128:
47784839
case Intrinsic::x86_avx_hsub_pd_256:
4779-
case Intrinsic::x86_avx_hsub_ps_256: {
4780-
handlePairwiseShadowOrIntrinsic(I, /*ReinterpretElemWidth=*/std::nullopt);
4840+
case Intrinsic::x86_avx_hsub_ps_256:
4841+
case Intrinsic::x86_avx2_phsub_d:
4842+
case Intrinsic::x86_avx2_phsub_w:
4843+
case Intrinsic::x86_avx2_phsub_sw: {
4844+
handleAVXHorizontalAddSubIntrinsic(I);
47814845
break;
47824846
}
47834847

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -435,9 +435,10 @@ define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1
435435
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
436436
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
437437
; CHECK-NEXT: call void @llvm.donothing()
438-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
439-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
440-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP3]], [[TMP4]]
438+
; CHECK-NEXT: [[A0:%.*]] = bitcast <4 x i64> [[TMP1]] to <4 x double>
439+
; CHECK-NEXT: [[A1:%.*]] = bitcast <4 x i64> [[TMP2]] to <4 x double>
440+
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> [[A0]], <4 x double> [[A1]])
441+
; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <4 x double> [[RES]] to <4 x i64>
441442
; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> [[A2:%.*]], <4 x double> [[A3:%.*]])
442443
; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8
443444
; CHECK-NEXT: ret <4 x double> [[RES1]]
@@ -453,9 +454,10 @@ define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) #
453454
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
454455
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
455456
; CHECK-NEXT: call void @llvm.donothing()
456-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
457-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
458-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP3]], [[TMP4]]
457+
; CHECK-NEXT: [[A0:%.*]] = bitcast <8 x i32> [[TMP1]] to <8 x float>
458+
; CHECK-NEXT: [[A1:%.*]] = bitcast <8 x i32> [[TMP2]] to <8 x float>
459+
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])
460+
; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <8 x float> [[RES]] to <8 x i32>
459461
; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> [[A2:%.*]], <8 x float> [[A3:%.*]])
460462
; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
461463
; CHECK-NEXT: ret <8 x float> [[RES1]]
@@ -471,9 +473,10 @@ define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1
471473
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
472474
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
473475
; CHECK-NEXT: call void @llvm.donothing()
474-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
475-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> [[TMP2]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
476-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP3]], [[TMP4]]
476+
; CHECK-NEXT: [[A0:%.*]] = bitcast <4 x i64> [[TMP1]] to <4 x double>
477+
; CHECK-NEXT: [[A1:%.*]] = bitcast <4 x i64> [[TMP2]] to <4 x double>
478+
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> [[A0]], <4 x double> [[A1]])
479+
; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <4 x double> [[RES]] to <4 x i64>
477480
; CHECK-NEXT: [[RES1:%.*]] = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> [[A2:%.*]], <4 x double> [[A3:%.*]])
478481
; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8
479482
; CHECK-NEXT: ret <4 x double> [[RES1]]
@@ -489,9 +492,10 @@ define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) #
489492
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
490493
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
491494
; CHECK-NEXT: call void @llvm.donothing()
492-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
493-
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
494-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP3]], [[TMP4]]
495+
; CHECK-NEXT: [[A0:%.*]] = bitcast <8 x i32> [[TMP1]] to <8 x float>
496+
; CHECK-NEXT: [[A1:%.*]] = bitcast <8 x i32> [[TMP2]] to <8 x float>
497+
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> [[A0]], <8 x float> [[A1]])
498+
; CHECK-NEXT: [[_MSPROP:%.*]] = bitcast <8 x float> [[RES]] to <8 x i32>
495499
; CHECK-NEXT: [[RES1:%.*]] = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> [[A2:%.*]], <8 x float> [[A3:%.*]])
496500
; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
497501
; CHECK-NEXT: ret <8 x float> [[RES1]]

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll

Lines changed: 6 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -569,9 +569,7 @@ define <8 x i32> @test_x86_avx2_phadd_d(<8 x i32> %a0, <8 x i32> %a1) #0 {
569569
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
570570
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
571571
; CHECK-NEXT: call void @llvm.donothing()
572-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
573-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
574-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]
572+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> [[TMP1]], <8 x i32> [[TMP2]])
575573
; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])
576574
; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
577575
; CHECK-NEXT: ret <8 x i32> [[RES]]
@@ -587,9 +585,7 @@ define <16 x i16> @test_x86_avx2_phadd_sw(<16 x i16> %a0, <16 x i16> %a1) #0 {
587585
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8
588586
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
589587
; CHECK-NEXT: call void @llvm.donothing()
590-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
591-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
592-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]
588+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
593589
; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
594590
; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
595591
; CHECK-NEXT: ret <16 x i16> [[RES]]
@@ -605,9 +601,7 @@ define <16 x i16> @test_x86_avx2_phadd_w(<16 x i16> %a0, <16 x i16> %a1) #0 {
605601
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8
606602
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
607603
; CHECK-NEXT: call void @llvm.donothing()
608-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
609-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
610-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]
604+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
611605
; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
612606
; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
613607
; CHECK-NEXT: ret <16 x i16> [[RES]]
@@ -623,9 +617,7 @@ define <8 x i32> @test_x86_avx2_phsub_d(<8 x i32> %a0, <8 x i32> %a1) #0 {
623617
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
624618
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
625619
; CHECK-NEXT: call void @llvm.donothing()
626-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
627-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
628-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP9]], [[TMP10]]
620+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> [[TMP1]], <8 x i32> [[TMP2]])
629621
; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]])
630622
; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
631623
; CHECK-NEXT: ret <8 x i32> [[RES]]
@@ -641,9 +633,7 @@ define <16 x i16> @test_x86_avx2_phsub_sw(<16 x i16> %a0, <16 x i16> %a1) #0 {
641633
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8
642634
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
643635
; CHECK-NEXT: call void @llvm.donothing()
644-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
645-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
646-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]
636+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
647637
; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
648638
; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
649639
; CHECK-NEXT: ret <16 x i16> [[RES]]
@@ -659,9 +649,7 @@ define <16 x i16> @test_x86_avx2_phsub_w(<16 x i16> %a0, <16 x i16> %a1) #0 {
659649
; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8
660650
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
661651
; CHECK-NEXT: call void @llvm.donothing()
662-
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
663-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
664-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP9]], [[TMP10]]
652+
; CHECK-NEXT: [[_MSPROP:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
665653
; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]])
666654
; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8
667655
; CHECK-NEXT: ret <16 x i16> [[RES]]

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