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andreisfrantmak
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[Xtensa] Lowering GLobalTLSAddress operation.
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5 files changed

+57
-3
lines changed

5 files changed

+57
-3
lines changed

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,10 +46,14 @@ XtensaObjectWriter::~XtensaObjectWriter() {}
4646
unsigned XtensaObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
4747
const MCFixup &Fixup,
4848
bool IsPCRel) const {
49+
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();
4950

5051
switch ((unsigned)Fixup.getKind()) {
5152
case FK_Data_4:
52-
return ELF::R_XTENSA_32;
53+
if (Modifier == MCSymbolRefExpr::VariantKind::VK_TPOFF)
54+
return ELF::R_XTENSA_TLS_TPOFF;
55+
else
56+
return ELF::R_XTENSA_32;
5357
default:
5458
return ELF::R_XTENSA_SLOT0_OP;
5559
}

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 43 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
6767
setStackPointerRegisterToSaveRestore(Xtensa::SP);
6868

6969
setSchedulingPreference(Sched::RegPressure);
70-
70+
7171
setBooleanContents(ZeroOrOneBooleanContent);
7272
setBooleanVectorContents(ZeroOrOneBooleanContent);
7373

@@ -88,6 +88,7 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
8888
// Handle the various types of symbolic address.
8989
setOperationAction(ISD::ConstantPool, PtrVT, Custom);
9090
setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
91+
setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
9192
setOperationAction(ISD::BlockAddress, PtrVT, Custom);
9293
setOperationAction(ISD::JumpTable, PtrVT, Custom);
9394

@@ -1298,6 +1299,44 @@ SDValue XtensaTargetLowering::LowerGlobalAddress(SDValue Op,
12981299
llvm_unreachable("invalid global addresses to lower");
12991300
}
13001301

1302+
SDValue XtensaTargetLowering::LowerGlobalTLSAddress(GlobalAddressSDNode *GA,
1303+
SelectionDAG &DAG) const {
1304+
SDLoc DL(GA);
1305+
const GlobalValue *GV = GA->getGlobal();
1306+
EVT PtrVT = getPointerTy(DAG.getDataLayout());
1307+
1308+
if (DAG.getTarget().useEmulatedTLS())
1309+
return LowerToTLSEmulatedModel(GA, DAG);
1310+
1311+
TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1312+
1313+
if (!Subtarget.hasTHREADPTR()) {
1314+
llvm_unreachable("only emulated TLS supported");
1315+
}
1316+
1317+
if ((model == TLSModel::LocalExec) || (model == TLSModel::InitialExec)) {
1318+
auto PtrVt = getPointerTy(DAG.getDataLayout());
1319+
1320+
bool Priv = GV->isPrivateLinkage(GV->getLinkage());
1321+
// Create a constant pool entry for the callee address
1322+
XtensaConstantPoolValue *CPV = XtensaConstantPoolSymbol::Create(
1323+
*DAG.getContext(), GV->getName().str().c_str() /* Sym */,
1324+
0 /* XtensaCLabelIndex */, Priv, XtensaCP::TPOFF);
1325+
1326+
// Get the address of the callee into a register
1327+
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1328+
SDValue CPWrap = getAddrPCRel(CPAddr, DAG);
1329+
1330+
SDValue TPRegister = DAG.getRegister(Xtensa::THREADPTR, MVT::i32);
1331+
SDValue ThreadPointer =
1332+
DAG.getNode(XtensaISD::RUR, DL, MVT::i32, TPRegister);
1333+
return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, CPWrap);
1334+
} else
1335+
llvm_unreachable("only local-exec and initial-exec TLS mode supported");
1336+
1337+
return SDValue();
1338+
}
1339+
13011340
SDValue XtensaTargetLowering::LowerBlockAddress(BlockAddressSDNode *Node,
13021341
SelectionDAG &DAG) const {
13031342
const BlockAddress *BA = Node->getBlockAddress();
@@ -1629,6 +1668,8 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
16291668
return LowerSELECT_CC(Op, DAG);
16301669
case ISD::GlobalAddress:
16311670
return LowerGlobalAddress(Op, DAG);
1671+
case ISD::GlobalTLSAddress:
1672+
return LowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
16321673
case ISD::BlockAddress:
16331674
return LowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
16341675
case ISD::JumpTable:
@@ -1685,6 +1726,7 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
16851726
OPCODE(MSUB);
16861727
OPCODE(MOVS);
16871728
OPCODE(MOVSP);
1729+
OPCODE(RUR);
16881730
OPCODE(SHL);
16891731
OPCODE(SRA);
16901732
OPCODE(SRL);

llvm/lib/Target/Xtensa/XtensaISelLowering.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@ enum {
6363
// WinABI Return
6464
RETW_FLAG,
6565

66+
RUR,
67+
6668
// Selects between operand 0 and operand 1. Operand 2 is the
6769
// mask of condition-code values for which operand 0 should be
6870
// chosen over operand 1; it has the same form as BR_CCMASK.
@@ -166,6 +168,8 @@ class XtensaTargetLowering : public TargetLowering {
166168
SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;
167169
SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const;
168170
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
171+
SDValue LowerGlobalTLSAddress(GlobalAddressSDNode *Node,
172+
SelectionDAG &DAG) const;
169173
SDValue LowerBlockAddress(BlockAddressSDNode *Node, SelectionDAG &DAG) const;
170174
SDValue LowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
171175
SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;

llvm/lib/Target/Xtensa/XtensaInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -684,7 +684,7 @@ def WUR: RRR_Inst<0x00, 0x03, 0x0F, (outs UR:$ur), (ins AR:$t),
684684
}
685685

686686
def RUR: RRR_Inst<0x00, 0x03, 0x0E, (outs AR:$r), (ins UR:$ur),
687-
"rur\t$r, $ur", []>
687+
"rur\t$r, $ur", [(set AR:$r, (Xtensa_rur UR:$ur))]>
688688
{
689689
bits<8> ur;
690690

llvm/lib/Target/Xtensa/XtensaOperators.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ def SDT_XtensaSRC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCi
4040
SDTCisVT<2, i32>]>;
4141
def SDT_XtensaSSL : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
4242
def SDT_XtensaSSR : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
43+
def SDT_XtensaRUR : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
4344

4445
//===----------------------------------------------------------------------===//
4546
// Node definitions
@@ -97,3 +98,6 @@ def Xtensa_ssr: SDNode<"XtensaISD::SSR", SDT_XtensaSSR, [SDNPOutGlue]>;
9798
def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>;
9899
def Xtensa_callw: SDNode<"XtensaISD::CALLW", SDT_XtensaCall,
99100
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
101+
102+
def Xtensa_rur: SDNode<"XtensaISD::RUR", SDT_XtensaRUR,
103+
[SDNPInGlue]>;

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