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fixup! Add a pseudo MV instruction for copy so we can compress it.
1 parent be725f5 commit 3f61dbb

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10 files changed

+81
-58
lines changed

10 files changed

+81
-58
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ class RISCVExpandPseudo : public MachineFunctionPass {
4848
MachineBasicBlock::iterator &NextMBBI);
4949
bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
5050
MachineBasicBlock::iterator MBBI, unsigned Opcode);
51+
bool expandMV_FPR16INX(MachineBasicBlock &MBB,
52+
MachineBasicBlock::iterator MBBI);
5153
bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
5254
MachineBasicBlock::iterator MBBI);
5355
bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
@@ -104,6 +106,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
104106
// expanded instructions for each pseudo is correct in the Size field of the
105107
// tablegen definition for the pseudo.
106108
switch (MBBI->getOpcode()) {
109+
case RISCV::PseudoMV_FPR16INX:
110+
return expandMV_FPR16INX(MBB, MBBI);
107111
case RISCV::PseudoRV32ZdinxSD:
108112
return expandRV32ZdinxStore(MBB, MBBI);
109113
case RISCV::PseudoRV32ZdinxLD:
@@ -266,6 +270,23 @@ bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
266270
return true;
267271
}
268272

273+
bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
274+
MachineBasicBlock::iterator MBBI) {
275+
DebugLoc DL = MBBI->getDebugLoc();
276+
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
277+
Register DstReg = TRI->getMatchingSuperReg(
278+
MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
279+
Register SrcReg = TRI->getMatchingSuperReg(
280+
MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
281+
282+
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
283+
.addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
284+
.addImm(0);
285+
286+
MBBI->eraseFromParent(); // The pseudo instruction is gone now.
287+
return true;
288+
}
289+
269290
// This function expands the PseudoRV32ZdinxSD for storing a double-precision
270291
// floating-point value into memory by generating an equivalent instruction
271292
// sequence for RV32.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -463,19 +463,9 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
463463
}
464464

465465
if (RISCV::GPRF16RegClass.contains(DstReg, SrcReg)) {
466-
if (STI.hasStdExtZhinx()) {
467-
BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_H_INX), DstReg)
468-
.addReg(SrcReg, getKillRegState(KillSrc))
469-
.addReg(SrcReg, getKillRegState(KillSrc));
470-
return;
471-
}
472-
DstReg =
473-
TRI->getMatchingSuperReg(DstReg, RISCV::sub_16, &RISCV::GPRRegClass);
474-
SrcReg =
475-
TRI->getMatchingSuperReg(SrcReg, RISCV::sub_16, &RISCV::GPRRegClass);
476-
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
477-
.addReg(SrcReg, getKillRegState(KillSrc))
478-
.addImm(0);
466+
BuildMI(MBB, MBBI, DL, get(RISCV::PseudoMV_FPR16INX), DstReg)
467+
.addReg(SrcReg,
468+
getKillRegState(KillSrc) | getRenamableRegState(RenamableSrc));
479469
return;
480470
}
481471

@@ -1528,6 +1518,9 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
15281518
}
15291519

15301520
switch (Opcode) {
1521+
case RISCV::PseudoMV_FPR16INX:
1522+
// MV is always compressible.
1523+
return STI.hasStdExtCOrZca() ? 2 : 4;
15311524
case TargetOpcode::STACKMAP:
15321525
// The upper bound for a stackmap intrinsic is the full length of its shadow
15331526
return StackMapOpers(&MI).getNumPatchBytes();

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -543,8 +543,8 @@ class HStore_rr<bits<7> funct7, string opcodestr>
543543
}
544544

545545
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
546-
class ALU_ri<bits<3> funct3, string opcodestr>
547-
: RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
546+
class ALU_ri<bits<3> funct3, string opcodestr, DAGOperand rty = GPR>
547+
: RVInstI<funct3, OPC_OP_IMM, (outs rty:$rd), (ins rty:$rs1, simm12:$imm12),
548548
opcodestr, "$rd, $rs1, $imm12">,
549549
Sched<[WriteIALU, ReadIALU]>;
550550

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,13 @@ let Predicates = [HasStdExtZhinxmin], isCodeGenOnly = 1 in {
9393
def LH_INX : Load_ri<0b001, "lh", GPRF16>, Sched<[WriteLDH, ReadMemBase]>;
9494
def SH_INX : Store_rri<0b001, "sh", GPRF16>,
9595
Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
96+
97+
// ADDI with GPRF16 register class to use for copy. This should not be used as
98+
// general ADDI, so the immediate should always be zero.
99+
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1,
100+
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
101+
def PseudoMV_FPR16INX : Pseudo<(outs GPRF16:$rd), (ins GPRF16:$rs), []>,
102+
Sched<[WriteIALU, ReadIALU]>;
96103
}
97104

98105
foreach Ext = ZfhExts in {

‎llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
385385
return false;
386386
case RISCV::LB:
387387
case RISCV::LH:
388+
case RISCV::LH_INX:
388389
case RISCV::LW:
389390
case RISCV::LBU:
390391
case RISCV::LHU:
@@ -395,6 +396,7 @@ bool RISCVMergeBaseOffsetOpt::foldIntoMemoryOps(MachineInstr &Hi,
395396
case RISCV::FLD:
396397
case RISCV::SB:
397398
case RISCV::SH:
399+
case RISCV::SH_INX:
398400
case RISCV::SW:
399401
case RISCV::SD:
400402
case RISCV::FSH:

‎llvm/test/CodeGen/RISCV/half-imm.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -114,12 +114,12 @@ define half @half_positive_zero(ptr %pf) nounwind {
114114
;
115115
; RV32IZHINX-LABEL: half_positive_zero:
116116
; RV32IZHINX: # %bb.0:
117-
; RV32IZHINX-NEXT: fmv.h a0, zero
117+
; RV32IZHINX-NEXT: li a0, 0
118118
; RV32IZHINX-NEXT: ret
119119
;
120120
; RV64IZHINX-LABEL: half_positive_zero:
121121
; RV64IZHINX: # %bb.0:
122-
; RV64IZHINX-NEXT: fmv.h a0, zero
122+
; RV64IZHINX-NEXT: li a0, 0
123123
; RV64IZHINX-NEXT: ret
124124
;
125125
; CHECKIZFHMIN-LABEL: half_positive_zero:

‎llvm/test/CodeGen/RISCV/half-maximum-minimum.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ define half @fminimum_f16(half %a, half %b) nounwind {
3737
; CHECKIZHINX-LABEL: fminimum_f16:
3838
; CHECKIZHINX: # %bb.0:
3939
; CHECKIZHINX-NEXT: feq.h a3, a0, a0
40-
; CHECKIZHINX-NEXT: fmv.h a2, a1
40+
; CHECKIZHINX-NEXT: mv a2, a1
4141
; CHECKIZHINX-NEXT: beqz a3, .LBB0_3
4242
; CHECKIZHINX-NEXT: # %bb.1:
4343
; CHECKIZHINX-NEXT: feq.h a3, a1, a1
@@ -46,7 +46,7 @@ define half @fminimum_f16(half %a, half %b) nounwind {
4646
; CHECKIZHINX-NEXT: fmin.h a0, a0, a2
4747
; CHECKIZHINX-NEXT: ret
4848
; CHECKIZHINX-NEXT: .LBB0_3:
49-
; CHECKIZHINX-NEXT: fmv.h a2, a0
49+
; CHECKIZHINX-NEXT: mv a2, a0
5050
; CHECKIZHINX-NEXT: feq.h a3, a1, a1
5151
; CHECKIZHINX-NEXT: bnez a3, .LBB0_2
5252
; CHECKIZHINX-NEXT: .LBB0_4:
@@ -81,7 +81,7 @@ define half @fmaximum_f16(half %a, half %b) nounwind {
8181
; CHECKIZHINX-LABEL: fmaximum_f16:
8282
; CHECKIZHINX: # %bb.0:
8383
; CHECKIZHINX-NEXT: feq.h a3, a0, a0
84-
; CHECKIZHINX-NEXT: fmv.h a2, a1
84+
; CHECKIZHINX-NEXT: mv a2, a1
8585
; CHECKIZHINX-NEXT: beqz a3, .LBB1_3
8686
; CHECKIZHINX-NEXT: # %bb.1:
8787
; CHECKIZHINX-NEXT: feq.h a3, a1, a1
@@ -90,7 +90,7 @@ define half @fmaximum_f16(half %a, half %b) nounwind {
9090
; CHECKIZHINX-NEXT: fmax.h a0, a0, a2
9191
; CHECKIZHINX-NEXT: ret
9292
; CHECKIZHINX-NEXT: .LBB1_3:
93-
; CHECKIZHINX-NEXT: fmv.h a2, a0
93+
; CHECKIZHINX-NEXT: mv a2, a0
9494
; CHECKIZHINX-NEXT: feq.h a3, a1, a1
9595
; CHECKIZHINX-NEXT: bnez a3, .LBB1_2
9696
; CHECKIZHINX-NEXT: .LBB1_4:

‎llvm/test/CodeGen/RISCV/half-mem.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -292,7 +292,7 @@ define half @flh_stack(half %a) nounwind {
292292
; RV32IZHINX-NEXT: addi sp, sp, -16
293293
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
294294
; RV32IZHINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
295-
; RV32IZHINX-NEXT: fmv.h s0, a0
295+
; RV32IZHINX-NEXT: mv s0, a0
296296
; RV32IZHINX-NEXT: addi a0, sp, 4
297297
; RV32IZHINX-NEXT: call notdead
298298
; RV32IZHINX-NEXT: lh a0, 4(sp)
@@ -307,7 +307,7 @@ define half @flh_stack(half %a) nounwind {
307307
; RV64IZHINX-NEXT: addi sp, sp, -32
308308
; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
309309
; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
310-
; RV64IZHINX-NEXT: fmv.h s0, a0
310+
; RV64IZHINX-NEXT: mv s0, a0
311311
; RV64IZHINX-NEXT: addi a0, sp, 12
312312
; RV64IZHINX-NEXT: call notdead
313313
; RV64IZHINX-NEXT: lh a0, 12(sp)

‎llvm/test/CodeGen/RISCV/half-select-fcmp.ll

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ define half @select_fcmp_false(half %a, half %b) nounwind {
2424
;
2525
; CHECKIZHINX-LABEL: select_fcmp_false:
2626
; CHECKIZHINX: # %bb.0:
27-
; CHECKIZHINX-NEXT: fmv.h a0, a1
27+
; CHECKIZHINX-NEXT: mv a0, a1
2828
; CHECKIZHINX-NEXT: ret
2929
;
3030
; CHECKIZFHMIN-LABEL: select_fcmp_false:
@@ -56,7 +56,7 @@ define half @select_fcmp_oeq(half %a, half %b) nounwind {
5656
; CHECKIZHINX-NEXT: feq.h a2, a0, a1
5757
; CHECKIZHINX-NEXT: bnez a2, .LBB1_2
5858
; CHECKIZHINX-NEXT: # %bb.1:
59-
; CHECKIZHINX-NEXT: fmv.h a0, a1
59+
; CHECKIZHINX-NEXT: mv a0, a1
6060
; CHECKIZHINX-NEXT: .LBB1_2:
6161
; CHECKIZHINX-NEXT: ret
6262
;
@@ -101,7 +101,7 @@ define half @select_fcmp_ogt(half %a, half %b) nounwind {
101101
; CHECKIZHINX-NEXT: flt.h a2, a1, a0
102102
; CHECKIZHINX-NEXT: bnez a2, .LBB2_2
103103
; CHECKIZHINX-NEXT: # %bb.1:
104-
; CHECKIZHINX-NEXT: fmv.h a0, a1
104+
; CHECKIZHINX-NEXT: mv a0, a1
105105
; CHECKIZHINX-NEXT: .LBB2_2:
106106
; CHECKIZHINX-NEXT: ret
107107
;
@@ -146,7 +146,7 @@ define half @select_fcmp_oge(half %a, half %b) nounwind {
146146
; CHECKIZHINX-NEXT: fle.h a2, a1, a0
147147
; CHECKIZHINX-NEXT: bnez a2, .LBB3_2
148148
; CHECKIZHINX-NEXT: # %bb.1:
149-
; CHECKIZHINX-NEXT: fmv.h a0, a1
149+
; CHECKIZHINX-NEXT: mv a0, a1
150150
; CHECKIZHINX-NEXT: .LBB3_2:
151151
; CHECKIZHINX-NEXT: ret
152152
;
@@ -191,7 +191,7 @@ define half @select_fcmp_olt(half %a, half %b) nounwind {
191191
; CHECKIZHINX-NEXT: flt.h a2, a0, a1
192192
; CHECKIZHINX-NEXT: bnez a2, .LBB4_2
193193
; CHECKIZHINX-NEXT: # %bb.1:
194-
; CHECKIZHINX-NEXT: fmv.h a0, a1
194+
; CHECKIZHINX-NEXT: mv a0, a1
195195
; CHECKIZHINX-NEXT: .LBB4_2:
196196
; CHECKIZHINX-NEXT: ret
197197
;
@@ -236,7 +236,7 @@ define half @select_fcmp_ole(half %a, half %b) nounwind {
236236
; CHECKIZHINX-NEXT: fle.h a2, a0, a1
237237
; CHECKIZHINX-NEXT: bnez a2, .LBB5_2
238238
; CHECKIZHINX-NEXT: # %bb.1:
239-
; CHECKIZHINX-NEXT: fmv.h a0, a1
239+
; CHECKIZHINX-NEXT: mv a0, a1
240240
; CHECKIZHINX-NEXT: .LBB5_2:
241241
; CHECKIZHINX-NEXT: ret
242242
;
@@ -285,7 +285,7 @@ define half @select_fcmp_one(half %a, half %b) nounwind {
285285
; CHECKIZHINX-NEXT: or a2, a3, a2
286286
; CHECKIZHINX-NEXT: bnez a2, .LBB6_2
287287
; CHECKIZHINX-NEXT: # %bb.1:
288-
; CHECKIZHINX-NEXT: fmv.h a0, a1
288+
; CHECKIZHINX-NEXT: mv a0, a1
289289
; CHECKIZHINX-NEXT: .LBB6_2:
290290
; CHECKIZHINX-NEXT: ret
291291
;
@@ -338,7 +338,7 @@ define half @select_fcmp_ord(half %a, half %b) nounwind {
338338
; CHECKIZHINX-NEXT: and a2, a3, a2
339339
; CHECKIZHINX-NEXT: bnez a2, .LBB7_2
340340
; CHECKIZHINX-NEXT: # %bb.1:
341-
; CHECKIZHINX-NEXT: fmv.h a0, a1
341+
; CHECKIZHINX-NEXT: mv a0, a1
342342
; CHECKIZHINX-NEXT: .LBB7_2:
343343
; CHECKIZHINX-NEXT: ret
344344
;
@@ -391,7 +391,7 @@ define half @select_fcmp_ueq(half %a, half %b) nounwind {
391391
; CHECKIZHINX-NEXT: or a2, a3, a2
392392
; CHECKIZHINX-NEXT: beqz a2, .LBB8_2
393393
; CHECKIZHINX-NEXT: # %bb.1:
394-
; CHECKIZHINX-NEXT: fmv.h a0, a1
394+
; CHECKIZHINX-NEXT: mv a0, a1
395395
; CHECKIZHINX-NEXT: .LBB8_2:
396396
; CHECKIZHINX-NEXT: ret
397397
;
@@ -440,7 +440,7 @@ define half @select_fcmp_ugt(half %a, half %b) nounwind {
440440
; CHECKIZHINX-NEXT: fle.h a2, a0, a1
441441
; CHECKIZHINX-NEXT: beqz a2, .LBB9_2
442442
; CHECKIZHINX-NEXT: # %bb.1:
443-
; CHECKIZHINX-NEXT: fmv.h a0, a1
443+
; CHECKIZHINX-NEXT: mv a0, a1
444444
; CHECKIZHINX-NEXT: .LBB9_2:
445445
; CHECKIZHINX-NEXT: ret
446446
;
@@ -485,7 +485,7 @@ define half @select_fcmp_uge(half %a, half %b) nounwind {
485485
; CHECKIZHINX-NEXT: flt.h a2, a0, a1
486486
; CHECKIZHINX-NEXT: beqz a2, .LBB10_2
487487
; CHECKIZHINX-NEXT: # %bb.1:
488-
; CHECKIZHINX-NEXT: fmv.h a0, a1
488+
; CHECKIZHINX-NEXT: mv a0, a1
489489
; CHECKIZHINX-NEXT: .LBB10_2:
490490
; CHECKIZHINX-NEXT: ret
491491
;
@@ -530,7 +530,7 @@ define half @select_fcmp_ult(half %a, half %b) nounwind {
530530
; CHECKIZHINX-NEXT: fle.h a2, a1, a0
531531
; CHECKIZHINX-NEXT: beqz a2, .LBB11_2
532532
; CHECKIZHINX-NEXT: # %bb.1:
533-
; CHECKIZHINX-NEXT: fmv.h a0, a1
533+
; CHECKIZHINX-NEXT: mv a0, a1
534534
; CHECKIZHINX-NEXT: .LBB11_2:
535535
; CHECKIZHINX-NEXT: ret
536536
;
@@ -575,7 +575,7 @@ define half @select_fcmp_ule(half %a, half %b) nounwind {
575575
; CHECKIZHINX-NEXT: flt.h a2, a1, a0
576576
; CHECKIZHINX-NEXT: beqz a2, .LBB12_2
577577
; CHECKIZHINX-NEXT: # %bb.1:
578-
; CHECKIZHINX-NEXT: fmv.h a0, a1
578+
; CHECKIZHINX-NEXT: mv a0, a1
579579
; CHECKIZHINX-NEXT: .LBB12_2:
580580
; CHECKIZHINX-NEXT: ret
581581
;
@@ -620,7 +620,7 @@ define half @select_fcmp_une(half %a, half %b) nounwind {
620620
; CHECKIZHINX-NEXT: feq.h a2, a0, a1
621621
; CHECKIZHINX-NEXT: beqz a2, .LBB13_2
622622
; CHECKIZHINX-NEXT: # %bb.1:
623-
; CHECKIZHINX-NEXT: fmv.h a0, a1
623+
; CHECKIZHINX-NEXT: mv a0, a1
624624
; CHECKIZHINX-NEXT: .LBB13_2:
625625
; CHECKIZHINX-NEXT: ret
626626
;
@@ -669,7 +669,7 @@ define half @select_fcmp_uno(half %a, half %b) nounwind {
669669
; CHECKIZHINX-NEXT: and a2, a3, a2
670670
; CHECKIZHINX-NEXT: beqz a2, .LBB14_2
671671
; CHECKIZHINX-NEXT: # %bb.1:
672-
; CHECKIZHINX-NEXT: fmv.h a0, a1
672+
; CHECKIZHINX-NEXT: mv a0, a1
673673
; CHECKIZHINX-NEXT: .LBB14_2:
674674
; CHECKIZHINX-NEXT: ret
675675
;

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