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[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (llvm#141101)
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114 files changed

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‎llvm/include/llvm/CodeGen/PeepholeOptimizer.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,7 @@ class PeepholeOptimizerPass : public PassInfoMixin<PeepholeOptimizerPass> {
1919
MachineFunctionAnalysisManager &MFAM);
2020

2121
MachineFunctionProperties getRequiredProperties() const {
22-
return MachineFunctionProperties().set(
23-
MachineFunctionProperties::Property::IsSSA);
22+
return MachineFunctionProperties().setIsSSA();
2423
}
2524
};
2625

‎llvm/lib/Passes/PassBuilder.cpp

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -448,7 +448,7 @@ class TriggerVerifierErrorPass
448448
// Intentionally create a virtual register and set NoVRegs property.
449449
auto &MRI = MF.getRegInfo();
450450
MRI.createGenericVirtualRegister(LLT::scalar(8));
451-
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
451+
MF.getProperties().setNoVRegs();
452452
return PreservedAnalyses::all();
453453
}
454454

@@ -466,19 +466,18 @@ class RequireAllMachineFunctionPropertiesPass
466466
}
467467

468468
static MachineFunctionProperties getRequiredProperties() {
469-
MachineFunctionProperties MFProps;
470-
MFProps.set(MachineFunctionProperties::Property::FailedISel);
471-
MFProps.set(MachineFunctionProperties::Property::FailsVerification);
472-
MFProps.set(MachineFunctionProperties::Property::IsSSA);
473-
MFProps.set(MachineFunctionProperties::Property::Legalized);
474-
MFProps.set(MachineFunctionProperties::Property::NoPHIs);
475-
MFProps.set(MachineFunctionProperties::Property::NoVRegs);
476-
MFProps.set(MachineFunctionProperties::Property::RegBankSelected);
477-
MFProps.set(MachineFunctionProperties::Property::Selected);
478-
MFProps.set(MachineFunctionProperties::Property::TiedOpsRewritten);
479-
MFProps.set(MachineFunctionProperties::Property::TracksDebugUserValues);
480-
MFProps.set(MachineFunctionProperties::Property::TracksLiveness);
481-
return MFProps;
469+
return MachineFunctionProperties()
470+
.setFailedISel()
471+
.setFailsVerification()
472+
.setIsSSA()
473+
.setLegalized()
474+
.setNoPHIs()
475+
.setNoVRegs()
476+
.setRegBankSelected()
477+
.setSelected()
478+
.setTiedOpsRewritten()
479+
.setTracksDebugUserValues()
480+
.setTracksLiveness();
482481
}
483482
static StringRef name() { return "RequireAllMachineFunctionPropertiesPass"; }
484483
};

‎llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,8 +86,7 @@ class AArch64A53Fix835769 : public MachineFunctionPass {
8686
bool runOnMachineFunction(MachineFunction &F) override;
8787

8888
MachineFunctionProperties getRequiredProperties() const override {
89-
return MachineFunctionProperties().set(
90-
MachineFunctionProperties::Property::NoVRegs);
89+
return MachineFunctionProperties().setNoVRegs();
9190
}
9291

9392
StringRef getPassName() const override {

‎llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,8 +117,7 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
117117
bool runOnMachineFunction(MachineFunction &F) override;
118118

119119
MachineFunctionProperties getRequiredProperties() const override {
120-
return MachineFunctionProperties().set(
121-
MachineFunctionProperties::Property::NoVRegs);
120+
return MachineFunctionProperties().setNoVRegs();
122121
}
123122

124123
StringRef getPassName() const override {

‎llvm/lib/Target/AArch64/AArch64CollectLOH.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,8 +132,7 @@ struct AArch64CollectLOH : public MachineFunctionPass {
132132
bool runOnMachineFunction(MachineFunction &MF) override;
133133

134134
MachineFunctionProperties getRequiredProperties() const override {
135-
return MachineFunctionProperties().set(
136-
MachineFunctionProperties::Property::NoVRegs);
135+
return MachineFunctionProperties().setNoVRegs();
137136
}
138137

139138
StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }

‎llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,7 @@ class AArch64CompressJumpTables : public MachineFunctionPass {
5252
bool runOnMachineFunction(MachineFunction &MF) override;
5353

5454
MachineFunctionProperties getRequiredProperties() const override {
55-
return MachineFunctionProperties().set(
56-
MachineFunctionProperties::Property::NoVRegs);
55+
return MachineFunctionProperties().setNoVRegs();
5756
}
5857
StringRef getPassName() const override {
5958
return "AArch64 Compress Jump Tables";

‎llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -188,8 +188,7 @@ class FalkorHWPFFix : public MachineFunctionPass {
188188
}
189189

190190
MachineFunctionProperties getRequiredProperties() const override {
191-
return MachineFunctionProperties().set(
192-
MachineFunctionProperties::Property::NoVRegs);
191+
return MachineFunctionProperties().setNoVRegs();
193192
}
194193

195194
private:

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1121,7 +1121,7 @@ let RecomputePerFunction = 1 in {
11211121
// SelectionDAG's behaviour.
11221122
// FIXME: One day there will probably be a nicer way to check for this, but
11231123
// today is not that day.
1124-
def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">;
1124+
def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">;
11251125
}
11261126

11271127
include "AArch64InstrFormats.td"

‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -233,8 +233,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
233233
bool runOnMachineFunction(MachineFunction &Fn) override;
234234

235235
MachineFunctionProperties getRequiredProperties() const override {
236-
return MachineFunctionProperties().set(
237-
MachineFunctionProperties::Property::NoVRegs);
236+
return MachineFunctionProperties().setNoVRegs();
238237
}
239238

240239
StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }

‎llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,9 +173,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M,
173173

174174
MachineFunction &MF = MMI->getOrCreateMachineFunction(*F);
175175
// Remove unnecessary register liveness and set NoVRegs.
176-
MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness);
177-
MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
178-
MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
176+
MF.getProperties().resetTracksLiveness().resetIsSSA().setNoVRegs();
179177
MF.getRegInfo().freezeReservedRegs();
180178

181179
// Create entry block.

‎llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -92,8 +92,7 @@ class AArch64RedundantCopyElimination : public MachineFunctionPass {
9292
bool optimizeBlock(MachineBasicBlock *MBB);
9393
bool runOnMachineFunction(MachineFunction &MF) override;
9494
MachineFunctionProperties getRequiredProperties() const override {
95-
return MachineFunctionProperties().set(
96-
MachineFunctionProperties::Property::NoVRegs);
95+
return MachineFunctionProperties().setNoVRegs();
9796
}
9897
StringRef getPassName() const override {
9998
return "AArch64 Redundant Copy Elimination";

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -544,8 +544,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
544544
// the pipeline since it prevents other infrastructure from reasoning about
545545
// it's liveness. We use the NoVRegs property instead of IsSSA because
546546
// IsSSA is removed before VirtRegRewriter runs.
547-
if (!MF.getProperties().hasProperty(
548-
MachineFunctionProperties::Property::NoVRegs))
547+
if (!MF.getProperties().hasNoVRegs())
549548
markSuperRegs(Reserved, AArch64::LR);
550549
}
551550

‎llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,8 +147,7 @@ AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner()
147147
}
148148

149149
bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
150-
if (MF.getProperties().hasProperty(
151-
MachineFunctionProperties::Property::FailedISel))
150+
if (MF.getProperties().hasFailedISel())
152151
return false;
153152
auto &TPC = getAnalysis<TargetPassConfig>();
154153

‎llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -654,12 +654,9 @@ AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
654654
}
655655

656656
bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
657-
if (MF.getProperties().hasProperty(
658-
MachineFunctionProperties::Property::FailedISel))
657+
if (MF.getProperties().hasFailedISel())
659658
return false;
660-
assert(MF.getProperties().hasProperty(
661-
MachineFunctionProperties::Property::Legalized) &&
662-
"Expected a legalized function?");
659+
assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
663660
auto *TPC = &getAnalysis<TargetPassConfig>();
664661
const Function &F = MF.getFunction();
665662
bool EnableOpt =

‎llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1257,12 +1257,9 @@ AArch64PostLegalizerLowering::AArch64PostLegalizerLowering()
12571257
}
12581258

12591259
bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) {
1260-
if (MF.getProperties().hasProperty(
1261-
MachineFunctionProperties::Property::FailedISel))
1260+
if (MF.getProperties().hasFailedISel())
12621261
return false;
1263-
assert(MF.getProperties().hasProperty(
1264-
MachineFunctionProperties::Property::Legalized) &&
1265-
"Expected a legalized function?");
1262+
assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
12661263
auto *TPC = &getAnalysis<TargetPassConfig>();
12671264
const Function &F = MF.getFunction();
12681265

‎llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -292,12 +292,9 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
292292
}
293293

294294
bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) {
295-
if (MF.getProperties().hasProperty(
296-
MachineFunctionProperties::Property::FailedISel))
295+
if (MF.getProperties().hasFailedISel())
297296
return false;
298-
assert(MF.getProperties().hasProperty(
299-
MachineFunctionProperties::Property::Selected) &&
300-
"Expected a selected MF");
297+
assert(MF.getProperties().hasSelected() && "Expected a selected MF");
301298

302299
bool Changed = false;
303300
for (auto &BB : MF) {

‎llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -836,8 +836,7 @@ AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
836836
}
837837

838838
bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
839-
if (MF.getProperties().hasProperty(
840-
MachineFunctionProperties::Property::FailedISel))
839+
if (MF.getProperties().hasFailedISel())
841840
return false;
842841
auto &TPC = getAnalysis<TargetPassConfig>();
843842

‎llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -478,8 +478,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
478478
}
479479

480480
bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
481-
if (MF.getProperties().hasProperty(
482-
MachineFunctionProperties::Property::FailedISel))
481+
if (MF.getProperties().hasFailedISel())
483482
return false;
484483
auto *TPC = &getAnalysis<TargetPassConfig>();
485484
const Function &F = MF.getFunction();

‎llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -253,8 +253,7 @@ AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
253253
}
254254

255255
bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
256-
if (MF.getProperties().hasProperty(
257-
MachineFunctionProperties::Property::FailedISel))
256+
if (MF.getProperties().hasFailedISel())
258257
return false;
259258
auto *TPC = &getAnalysis<TargetPassConfig>();
260259
const Function &F = MF.getFunction();

‎llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -462,8 +462,7 @@ AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
462462
}
463463

464464
bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
465-
if (MF.getProperties().hasProperty(
466-
MachineFunctionProperties::Property::FailedISel))
465+
if (MF.getProperties().hasFailedISel())
467466
return false;
468467
auto *TPC = &getAnalysis<TargetPassConfig>();
469468
const Function &F = MF.getFunction();

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,7 @@ class AMDGPURegBankLegalize : public MachineFunctionPass {
5858
// If there were no phis and we do waterfall expansion machine verifier would
5959
// fail.
6060
MachineFunctionProperties getClearedProperties() const override {
61-
return MachineFunctionProperties().set(
62-
MachineFunctionProperties::Property::NoPHIs);
61+
return MachineFunctionProperties().setNoPHIs();
6362
}
6463
};
6564

@@ -250,8 +249,7 @@ class AMDGPURegBankLegalizeCombiner {
250249
}
251250

252251
bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
253-
if (MF.getProperties().hasProperty(
254-
MachineFunctionProperties::Property::FailedISel))
252+
if (MF.getProperties().hasFailedISel())
255253
return false;
256254

257255
// Setup the instruction builder with CSE.

‎llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,7 @@ class AMDGPURegBankSelect : public MachineFunctionPass {
5353
// This pass assigns register banks to all virtual registers, and we maintain
5454
// this property in subsequent passes
5555
MachineFunctionProperties getSetProperties() const override {
56-
return MachineFunctionProperties().set(
57-
MachineFunctionProperties::Property::RegBankSelected);
56+
return MachineFunctionProperties().setRegBankSelected();
5857
}
5958
};
6059

@@ -199,8 +198,7 @@ static Register getVReg(MachineOperand &Op) {
199198
}
200199

201200
bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
202-
if (MF.getProperties().hasProperty(
203-
MachineFunctionProperties::Property::FailedISel))
201+
if (MF.getProperties().hasFailedISel())
204202
return false;
205203

206204
// Setup the instruction builder with CSE.

‎llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,7 @@ class GCNDPPCombineLegacy : public MachineFunctionPass {
9898
}
9999

100100
MachineFunctionProperties getRequiredProperties() const override {
101-
return MachineFunctionProperties()
102-
.set(MachineFunctionProperties::Property::IsSSA);
101+
return MachineFunctionProperties().setIsSSA();
103102
}
104103
};
105104

‎llvm/lib/Target/AMDGPU/GCNDPPCombine.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,7 @@ class GCNDPPCombinePass : public PassInfoMixin<GCNDPPCombinePass> {
1818
MachineFunctionAnalysisManager &MAM);
1919

2020
MachineFunctionProperties getRequiredProperties() const {
21-
return MachineFunctionProperties().set(
22-
MachineFunctionProperties::Property::IsSSA);
21+
return MachineFunctionProperties().setIsSSA();
2322
}
2423
};
2524

‎llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,7 @@ class R600MachineCFGStructurizer : public MachineFunctionPass {
121121

122122
bool runOnMachineFunction(MachineFunction &MF) override {
123123
// FIXME: This pass causes verification failures.
124-
MF.getProperties().set(
125-
MachineFunctionProperties::Property::FailsVerification);
124+
MF.getProperties().setFailsVerification();
126125

127126
TII = MF.getSubtarget<R600Subtarget>().getInstrInfo();
128127
TRI = &TII->getRegisterInfo();

‎llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,7 @@ class R600VectorRegMerger : public MachineFunctionPass {
111111
}
112112

113113
MachineFunctionProperties getRequiredProperties() const override {
114-
return MachineFunctionProperties()
115-
.set(MachineFunctionProperties::Property::IsSSA);
114+
return MachineFunctionProperties().setIsSSA();
116115
}
117116

118117
StringRef getPassName() const override {

‎llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -618,8 +618,7 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
618618

619619
bool SIFixSGPRCopies::run(MachineFunction &MF) {
620620
// Only need to run this in SelectionDAG path.
621-
if (MF.getProperties().hasProperty(
622-
MachineFunctionProperties::Property::Selected))
621+
if (MF.getProperties().hasSelected())
623622
return false;
624623

625624
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -191,8 +191,7 @@ class SIFoldOperandsLegacy : public MachineFunctionPass {
191191
}
192192

193193
MachineFunctionProperties getRequiredProperties() const override {
194-
return MachineFunctionProperties().set(
195-
MachineFunctionProperties::Property::IsSSA);
194+
return MachineFunctionProperties().setIsSSA();
196195
}
197196
};
198197

‎llvm/lib/Target/AMDGPU/SIFoldOperands.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,7 @@ class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
1919
MachineFunctionAnalysisManager &MFAM);
2020

2121
MachineFunctionProperties getRequiredProperties() const {
22-
return MachineFunctionProperties().set(
23-
MachineFunctionProperties::Property::IsSSA);
22+
return MachineFunctionProperties().setIsSSA();
2423
}
2524
};
2625
} // namespace llvm

‎llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,7 @@ class SIFormMemoryClausesLegacy : public MachineFunctionPass {
7878
}
7979

8080
MachineFunctionProperties getClearedProperties() const override {
81-
return MachineFunctionProperties().set(
82-
MachineFunctionProperties::Property::IsSSA);
81+
return MachineFunctionProperties().setIsSSA();
8382
}
8483
};
8584

‎llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -323,8 +323,7 @@ class SILoadStoreOptimizerLegacy : public MachineFunctionPass {
323323
}
324324

325325
MachineFunctionProperties getRequiredProperties() const override {
326-
return MachineFunctionProperties()
327-
.set(MachineFunctionProperties::Property::IsSSA);
326+
return MachineFunctionProperties().setIsSSA();
328327
}
329328
};
330329

‎llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,7 @@ class SILoadStoreOptimizerPass
2020
MachineFunctionAnalysisManager &MFAM);
2121

2222
MachineFunctionProperties getRequiredProperties() const {
23-
return MachineFunctionProperties().set(
24-
MachineFunctionProperties::Property::IsSSA);
23+
return MachineFunctionProperties().setIsSSA();
2524
}
2625
};
2726

‎llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -859,8 +859,7 @@ void Vreg1LoweringHelper::constrainAsLaneMask(Incoming &In) {}
859859
static bool runFixI1Copies(MachineFunction &MF, MachineDominatorTree &MDT,
860860
MachinePostDominatorTree &MPDT) {
861861
// Only need to run this in SelectionDAG path.
862-
if (MF.getProperties().hasProperty(
863-
MachineFunctionProperties::Property::Selected))
862+
if (MF.getProperties().hasSelected())
864863
return false;
865864

866865
Vreg1LoweringHelper Helper(&MF, &MDT, &MPDT);

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