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[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (llvm#88954)
This is largely a revert of commit e817966. As llvm#88029 shows, there exists hardware that only supports unaligned scalar. I'm leaving how this gets exposed to the clang interface to a future patch.
1 parent 6cfa40e commit 5c5c575

21 files changed

+67
-47
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -352,7 +352,8 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
352352
if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
353353
HasLegalHalfType = true;
354354

355-
FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
355+
FastUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem") &&
356+
llvm::is_contained(Features, "+unaligned-vector-mem");
356357

357358
if (llvm::is_contained(Features, "+experimental"))
358359
HasExperimental = true;

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,10 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
6868
<< A->getSpelling() << Mcpu;
6969
}
7070

71-
if (llvm::RISCV::hasFastUnalignedAccess(Mcpu))
72-
Features.push_back("+fast-unaligned-access");
71+
if (llvm::RISCV::hasFastUnalignedAccess(Mcpu)) {
72+
Features.push_back("+unaligned-scalar-mem");
73+
Features.push_back("+unaligned-vector-mem");
74+
}
7375
}
7476

7577
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
@@ -169,7 +171,9 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
169171

170172
// -mno-unaligned-access is default, unless -munaligned-access is specified.
171173
AddTargetFeature(Args, Features, options::OPT_munaligned_access,
172-
options::OPT_mno_unaligned_access, "fast-unaligned-access");
174+
options::OPT_mno_unaligned_access, "unaligned-scalar-mem");
175+
AddTargetFeature(Args, Features, options::OPT_munaligned_access,
176+
options::OPT_mno_unaligned_access, "unaligned-vector-mem");
173177

174178
// Now add any that the user explicitly requested on the command line,
175179
// which may override the defaults.

‎clang/test/Driver/riscv-features.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@
3232
// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | FileCheck %s -check-prefix=FAST-UNALIGNED-ACCESS
3333
// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-FAST-UNALIGNED-ACCESS
3434

35-
// FAST-UNALIGNED-ACCESS: "-target-feature" "+fast-unaligned-access"
36-
// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-fast-unaligned-access"
35+
// FAST-UNALIGNED-ACCESS: "-target-feature" "+unaligned-scalar-mem" "-target-feature" "+unaligned-vector-mem"
36+
// NO-FAST-UNALIGNED-ACCESS: "-target-feature" "-unaligned-scalar-mem" "-target-feature" "-unaligned-vector-mem"
3737

3838
// RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
3939
// RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -317,8 +317,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
317317
.addReg(MBBI->getOperand(1).getReg())
318318
.add(MBBI->getOperand(2));
319319
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
320-
// FIXME: Zdinx RV32 can not work on unaligned memory.
321-
assert(!STI->hasFastUnalignedAccess());
320+
// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
321+
assert(!STI->enableUnalignedScalarMem());
322322

323323
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
324324
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1020,10 +1020,15 @@ def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
10201020
"true",
10211021
"Enable trailing fence for seq-cst store.">;
10221022

1023-
def FeatureFastUnalignedAccess
1024-
: SubtargetFeature<"fast-unaligned-access", "HasFastUnalignedAccess",
1025-
"true", "Has reasonably performant unaligned "
1026-
"loads and stores (both scalar and vector)">;
1023+
def FeatureUnalignedScalarMem
1024+
: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
1025+
"true", "Has reasonably performant unaligned scalar "
1026+
"loads and stores">;
1027+
1028+
def FeatureUnalignedVectorMem
1029+
: SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
1030+
"true", "Has reasonably performant unaligned vector "
1031+
"loads and stores">;
10271032

10281033
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
10291034
"UsePostRAScheduler", "true", "Schedule again after register allocation">;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1883,7 +1883,7 @@ bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
18831883
// replace. If we don't support unaligned scalar mem, prefer the constant
18841884
// pool.
18851885
// TODO: Can the caller pass down the alignment?
1886-
if (!Subtarget.hasFastUnalignedAccess())
1886+
if (!Subtarget.enableUnalignedScalarMem())
18871887
return true;
18881888

18891889
// Prefer to keep the load if it would require many instructions.
@@ -15101,7 +15101,7 @@ static bool matchIndexAsWiderOp(EVT VT, SDValue Index, SDValue Mask,
1510115101
if (WiderElementSize > ST.getELen()/8)
1510215102
return false;
1510315103

15104-
if (!ST.hasFastUnalignedAccess() && BaseAlign < WiderElementSize)
15104+
if (!ST.enableUnalignedVectorMem() && BaseAlign < WiderElementSize)
1510515105
return false;
1510615106

1510715107
for (unsigned i = 0; i < Index->getNumOperands(); i++) {
@@ -19772,8 +19772,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
1977219772
unsigned *Fast) const {
1977319773
if (!VT.isVector()) {
1977419774
if (Fast)
19775-
*Fast = Subtarget.hasFastUnalignedAccess();
19776-
return Subtarget.hasFastUnalignedAccess();
19775+
*Fast = Subtarget.enableUnalignedScalarMem();
19776+
return Subtarget.enableUnalignedScalarMem();
1977719777
}
1977819778

1977919779
// All vector implementations must support element alignment
@@ -19789,8 +19789,8 @@ bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
1978919789
// misaligned accesses. TODO: Work through the codegen implications of
1979019790
// allowing such accesses to be formed, and considered fast.
1979119791
if (Fast)
19792-
*Fast = Subtarget.hasFastUnalignedAccess();
19793-
return Subtarget.hasFastUnalignedAccess();
19792+
*Fast = Subtarget.enableUnalignedVectorMem();
19793+
return Subtarget.enableUnalignedVectorMem();
1979419794
}
1979519795

1979619796

@@ -19825,7 +19825,7 @@ EVT RISCVTargetLowering::getOptimalMemOpType(const MemOp &Op,
1982519825

1982619826
// Do we have sufficient alignment for our preferred VT? If not, revert
1982719827
// to largest size allowed by our alignment criteria.
19828-
if (PreferredVT != MVT::i8 && !Subtarget.hasFastUnalignedAccess()) {
19828+
if (PreferredVT != MVT::i8 && !Subtarget.enableUnalignedVectorMem()) {
1982919829
Align RequiredAlign(PreferredVT.getStoreSize());
1983019830
if (Op.isFixedDstAlign())
1983119831
RequiredAlign = std::min(RequiredAlign, Op.getDstAlign());
@@ -20017,7 +20017,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
2001720017
if (!isLegalElementTypeForRVV(ScalarType))
2001820018
return false;
2001920019

20020-
if (!Subtarget.hasFastUnalignedAccess() &&
20020+
if (!Subtarget.enableUnalignedVectorMem() &&
2002120021
Alignment < ScalarType.getStoreSize())
2002220022
return false;
2002320023

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,8 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
239239
FeatureStdExtZbb,
240240
FeatureStdExtZbs,
241241
FeatureStdExtZfhmin,
242-
FeatureFastUnalignedAccess],
242+
FeatureUnalignedScalarMem,
243+
FeatureUnalignedVectorMem],
243244
[TuneNoDefaultUnroll,
244245
TuneConditionalCompressedMoveFusion,
245246
TuneLUIADDIFusion,
@@ -276,7 +277,8 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
276277
FeatureStdExtZvkng,
277278
FeatureStdExtZvksc,
278279
FeatureStdExtZvksg,
279-
FeatureFastUnalignedAccess],
280+
FeatureUnalignedScalarMem,
281+
FeatureUnalignedVectorMem],
280282
[TuneNoDefaultUnroll,
281283
TuneConditionalCompressedMoveFusion,
282284
TuneLUIADDIFusion,

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
202202
return false;
203203

204204
EVT ElemType = DataTypeVT.getScalarType();
205-
if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
205+
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
206206
return false;
207207

208208
return TLI->isLegalElementTypeForRVV(ElemType);
@@ -227,7 +227,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
227227
return false;
228228

229229
EVT ElemType = DataTypeVT.getScalarType();
230-
if (!ST->hasFastUnalignedAccess() && Alignment < ElemType.getStoreSize())
230+
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
231231
return false;
232232

233233
return TLI->isLegalElementTypeForRVV(ElemType);

‎llvm/test/CodeGen/RISCV/memcpy-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010

1111
; ----------------------------------------------------------------------

‎llvm/test/CodeGen/RISCV/memcpy.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/memset-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+fast-unaligned-access \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+unaligned-scalar-mem \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+fast-unaligned-access \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+unaligned-scalar-mem \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/pr56110.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
3-
; RUN: llc < %s -mtriple=riscv32 -mattr=+fast-unaligned-access | FileCheck %s
3+
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem | FileCheck %s
44

55
define void @foo_set(ptr nocapture noundef %a, i32 noundef %v) {
66
; CHECK-LABEL: foo_set:

‎llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ entry:
3636
}
3737

3838
; CHECK-NOT: .option push
39-
define void @test5() "target-features"="+fast-unaligned-access" {
39+
define void @test5() "target-features"="+unaligned-scalar-mem" {
4040
; CHECK-LABEL: test5
4141
; CHECK-NOT: .option pop
4242
entry:

‎llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -mattr=+v,+fast-unaligned-access -target-abi=ilp32 \
2+
; RUN: llc -mtriple=riscv32 -mattr=+v,+unaligned-vector-mem -target-abi=ilp32 \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4-
; RUN: llc -mtriple=riscv64 -mattr=+v,+fast-unaligned-access -target-abi=lp64 \
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+unaligned-vector-mem -target-abi=lp64 \
55
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
66

77
define void @constant_forward_stride(ptr %s, ptr %d) {

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV32
33
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV64
4-
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+fast-unaligned-access -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+unaligned-vector-mem -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN
55

66
; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh,+zve64f,+zvl128b,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,ZVE64F
77

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=SLOW,RV32-SLOW
44
; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s \
55
; RUN: | FileCheck %s --check-prefixes=SLOW,RV64-SLOW
6-
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+fast-unaligned-access -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \
77
; RUN: | FileCheck %s --check-prefixes=FAST,RV32-FAST
8-
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+fast-unaligned-access -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+unaligned-vector-mem -verify-machineinstrs < %s \
99
; RUN: | FileCheck %s --check-prefixes=FAST,RV64-FAST
1010

1111
define <4 x i32> @load_v4i32_align1(ptr %ptr) {

‎llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+v \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+fast-unaligned-access \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+fast-unaligned-access \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010

1111
; ----------------------------------------------------------------------

‎llvm/test/CodeGen/RISCV/rvv/memset-inline.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32
44
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v \
55
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64
6-
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+fast-unaligned-access \
6+
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+unaligned-scalar-mem,,+unaligned-vector-mem \
77
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
8-
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+fast-unaligned-access \
8+
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+unaligned-scalar-mem,+unaligned-vector-mem \
99
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
1010
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
1111

‎llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: -verify-machineinstrs | FileCheck %s
44
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v < %s \
55
; RUN: -verify-machineinstrs | FileCheck %s
6-
; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v,+fast-unaligned-access < %s \
6+
; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \
77
; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s
8-
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v,+fast-unaligned-access < %s \
8+
; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \
99
; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s
1010

1111

‎llvm/test/CodeGen/RISCV/unaligned-load-store.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@
33
; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV32I %s
44
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=ALL,SLOW,RV64I %s
6-
; RUN: llc -mtriple=riscv32 -mattr=+fast-unaligned-access -verify-machineinstrs < %s \
6+
; RUN: llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
77
; RUN: | FileCheck -check-prefixes=ALL,FAST,RV32I-FAST %s
8-
; RUN: llc -mtriple=riscv64 -mattr=+fast-unaligned-access -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=ALL,FAST,RV64I-FAST %s
1010

1111
; A collection of cases showing codegen for unaligned loads and stores

‎llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,11 +60,19 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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if (MArch.empty())
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MArch = getMArch(*Rec);
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const bool FastUnalignedAccess =
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bool FastScalarUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "fast-unaligned-access";
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return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
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});
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bool FastVectorUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "unaligned-vector-mem";
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});
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bool FastUnalignedAccess =
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FastScalarUnalignedAccess && FastVectorUnalignedAccess;
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OS << "PROC(" << Rec->getName() << ", "
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<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
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<< "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";

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