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[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister.
NVPTX, SPIRV, and WebAssembly pass virtual registers to this function since they don't perform register allocation. We need to use Register to avoid a virtual register being converted to MCRegister by the caller. This is an alternative to llvm#128456.
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57 files changed

+92
-93
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1035,7 +1035,7 @@ class TargetInstrInfo : public MCInstrInfo {
10351035
/// marked renamable.
10361036
virtual void copyPhysReg(MachineBasicBlock &MBB,
10371037
MachineBasicBlock::iterator MI, const DebugLoc &DL,
1038-
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
1038+
Register DestReg, Register SrcReg, bool KillSrc,
10391039
bool RenamableDest = false,
10401040
bool RenamableSrc = false) const {
10411041
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4988,8 +4988,8 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
49884988

49894989
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
49904990
MachineBasicBlock::iterator I,
4991-
const DebugLoc &DL, MCRegister DestReg,
4992-
MCRegister SrcReg, bool KillSrc,
4991+
const DebugLoc &DL, Register DestReg,
4992+
Register SrcReg, bool KillSrc,
49934993
bool RenamableDest,
49944994
bool RenamableSrc) const {
49954995
if (AArch64::GPR32spRegClass.contains(DestReg) &&
@@ -5068,8 +5068,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50685068
auto ToPPR = [](MCRegister R) -> MCRegister {
50695069
return (R - AArch64::PN0) + AArch64::P0;
50705070
};
5071-
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg;
5072-
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg;
5071+
MCRegister PPRSrcReg = SrcIsPNR ? ToPPR(SrcReg) : SrcReg.asMCReg();
5072+
MCRegister PPRDestReg = DestIsPNR ? ToPPR(DestReg) : DestReg.asMCReg();
50735073

50745074
if (PPRSrcReg != PPRDestReg) {
50755075
auto NewMI = BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), PPRDestReg)

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
343343
bool KillSrc, unsigned Opcode, unsigned ZeroReg,
344344
llvm::ArrayRef<unsigned> Indices) const;
345345
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
346-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
346+
const DebugLoc &DL, Register DestReg, Register SrcReg,
347347
bool KillSrc, bool RenamableDest = false,
348348
bool RenamableSrc = false) const override;
349349

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
3737

3838
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3939
MachineBasicBlock::iterator MI,
40-
const DebugLoc &DL, MCRegister DestReg,
41-
MCRegister SrcReg, bool KillSrc,
40+
const DebugLoc &DL, Register DestReg,
41+
Register SrcReg, bool KillSrc,
4242
bool RenamableDest, bool RenamableSrc) const {
4343
unsigned VectorComponents = 0;
4444
if ((R600::R600_Reg128RegClass.contains(DestReg) ||

‎llvm/lib/Target/AMDGPU/R600InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
7373
}
7474

7575
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
76-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76+
const DebugLoc &DL, Register DestReg, Register SrcReg,
7777
bool KillSrc, bool RenamableDest = false,
7878
bool RenamableSrc = false) const override;
7979
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -801,9 +801,9 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
801801

802802
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
803803
MachineBasicBlock::iterator MI,
804-
const DebugLoc &DL, MCRegister DestReg,
805-
MCRegister SrcReg, bool KillSrc,
806-
bool RenamableDest, bool RenamableSrc) const {
804+
const DebugLoc &DL, Register DestReg,
805+
Register SrcReg, bool KillSrc, bool RenamableDest,
806+
bool RenamableSrc) const {
807807
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
808808
unsigned Size = RI.getRegSizeInBits(*RC);
809809
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
@@ -816,7 +816,7 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
816816
if (((Size == 16) != (SrcSize == 16))) {
817817
// Non-VGPR Src and Dst will later be expanded back to 32 bits.
818818
assert(ST.hasTrue16BitInsts());
819-
MCRegister &RegToFix = (Size == 32) ? DestReg : SrcReg;
819+
Register &RegToFix = (Size == 32) ? DestReg : SrcReg;
820820
MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16);
821821
RegToFix = SubReg;
822822

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
263263
int64_t Offset1, unsigned NumLoads) const override;
264264

265265
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
266-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
266+
const DebugLoc &DL, Register DestReg, Register SrcReg,
267267
bool KillSrc, bool RenamableDest = false,
268268
bool RenamableSrc = false) const override;
269269

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
280280

281281
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
282282
MachineBasicBlock::iterator I,
283-
const DebugLoc &DL, MCRegister DestReg,
284-
MCRegister SrcReg, bool KillSrc,
283+
const DebugLoc &DL, Register DestReg,
284+
Register SrcReg, bool KillSrc,
285285
bool RenamableDest, bool RenamableSrc) const {
286286
assert(ARC::GPR32RegClass.contains(SrcReg) &&
287287
"Only GPR32 src copy supported.");

‎llvm/lib/Target/ARC/ARCInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6464
int *BytesRemoved = nullptr) const override;
6565

6666
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
67-
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
67+
const DebugLoc &, Register DestReg, Register SrcReg,
6868
bool KillSrc, bool RenamableDest = false,
6969
bool RenamableSrc = false) const override;
7070

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -889,8 +889,8 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
889889

890890
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
891891
MachineBasicBlock::iterator I,
892-
const DebugLoc &DL, MCRegister DestReg,
893-
MCRegister SrcReg, bool KillSrc,
892+
const DebugLoc &DL, Register DestReg,
893+
Register SrcReg, bool KillSrc,
894894
bool RenamableDest,
895895
bool RenamableSrc) const {
896896
bool GPRDest = ARM::GPRRegClass.contains(DestReg);

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
208208
const ARMSubtarget &Subtarget) const;
209209

210210
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
211-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
211+
const DebugLoc &DL, Register DestReg, Register SrcReg,
212212
bool KillSrc, bool RenamableDest = false,
213213
bool RenamableSrc = false) const override;
214214

‎llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
4141

4242
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4343
MachineBasicBlock::iterator I,
44-
const DebugLoc &DL, MCRegister DestReg,
45-
MCRegister SrcReg, bool KillSrc,
44+
const DebugLoc &DL, Register DestReg,
45+
Register SrcReg, bool KillSrc,
4646
bool RenamableDest, bool RenamableSrc) const {
4747
// Need to check the arch.
4848
MachineFunction &MF = *MBB.getParent();

‎llvm/lib/Target/ARM/Thumb1InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
3838
const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
3939

4040
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
41-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
41+
const DebugLoc &DL, Register DestReg, Register SrcReg,
4242
bool KillSrc, bool RenamableDest = false,
4343
bool RenamableSrc = false) const override;
4444
void storeRegToStackSlot(

‎llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
149149

150150
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
151151
MachineBasicBlock::iterator I,
152-
const DebugLoc &DL, MCRegister DestReg,
153-
MCRegister SrcReg, bool KillSrc,
152+
const DebugLoc &DL, Register DestReg,
153+
Register SrcReg, bool KillSrc,
154154
bool RenamableDest, bool RenamableSrc) const {
155155
// Handle SPR, DPR, and QPR copies.
156156
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))

‎llvm/lib/Target/ARM/Thumb2InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
3838
MachineBasicBlock::iterator MBBI) const override;
3939

4040
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
41-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
41+
const DebugLoc &DL, Register DestReg, Register SrcReg,
4242
bool KillSrc, bool RenamableDest = false,
4343
bool RenamableSrc = false) const override;
4444

‎llvm/lib/Target/AVR/AVRInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
3535

3636
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3737
MachineBasicBlock::iterator MI,
38-
const DebugLoc &DL, MCRegister DestReg,
39-
MCRegister SrcReg, bool KillSrc,
38+
const DebugLoc &DL, Register DestReg,
39+
Register SrcReg, bool KillSrc,
4040
bool RenamableDest, bool RenamableSrc) const {
4141
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
4242
unsigned Opc;

‎llvm/lib/Target/AVR/AVRInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ class AVRInstrInfo : public AVRGenInstrInfo {
7474
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
7575

7676
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
77-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
77+
const DebugLoc &DL, Register DestReg, Register SrcReg,
7878
bool KillSrc, bool RenamableDest = false,
7979
bool RenamableSrc = false) const override;
8080
void storeRegToStackSlot(

‎llvm/lib/Target/BPF/BPFInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ BPFInstrInfo::BPFInstrInfo()
3030

3131
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3232
MachineBasicBlock::iterator I,
33-
const DebugLoc &DL, MCRegister DestReg,
34-
MCRegister SrcReg, bool KillSrc,
33+
const DebugLoc &DL, Register DestReg,
34+
Register SrcReg, bool KillSrc,
3535
bool RenamableDest, bool RenamableSrc) const {
3636
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
3737
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)

‎llvm/lib/Target/BPF/BPFInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ class BPFInstrInfo : public BPFGenInstrInfo {
3030
const BPFRegisterInfo &getRegisterInfo() const { return RI; }
3131

3232
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
33-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
33+
const DebugLoc &DL, Register DestReg, Register SrcReg,
3434
bool KillSrc, bool RenamableDest = false,
3535
bool RenamableSrc = false) const override;
3636

‎llvm/lib/Target/CSKY/CSKYInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -476,8 +476,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(
476476

477477
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
478478
MachineBasicBlock::iterator I,
479-
const DebugLoc &DL, MCRegister DestReg,
480-
MCRegister SrcReg, bool KillSrc,
479+
const DebugLoc &DL, Register DestReg,
480+
Register SrcReg, bool KillSrc,
481481
bool RenamableDest, bool RenamableSrc) const {
482482
if (CSKY::GPRRegClass.contains(SrcReg) &&
483483
CSKY::CARRYRegClass.contains(DestReg)) {

‎llvm/lib/Target/CSKY/CSKYInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
5353
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
5454

5555
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
56-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
56+
const DebugLoc &DL, Register DestReg, Register SrcReg,
5757
bool KillSrc, bool RenamableDest = false,
5858
bool RenamableSrc = false) const override;
5959

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -858,8 +858,8 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
858858

859859
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
860860
MachineBasicBlock::iterator I,
861-
const DebugLoc &DL, MCRegister DestReg,
862-
MCRegister SrcReg, bool KillSrc,
861+
const DebugLoc &DL, Register DestReg,
862+
Register SrcReg, bool KillSrc,
863863
bool RenamableDest,
864864
bool RenamableSrc) const {
865865
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
173173
/// careful implementation when multiple copy instructions are required for
174174
/// large registers. See for example the ARM target.
175175
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
176-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
176+
const DebugLoc &DL, Register DestReg, Register SrcReg,
177177
bool KillSrc, bool RenamableDest = false,
178178
bool RenamableSrc = false) const override;
179179

‎llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ LanaiInstrInfo::LanaiInstrInfo()
3232
void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3333
MachineBasicBlock::iterator Position,
3434
const DebugLoc &DL,
35-
MCRegister DestinationRegister,
36-
MCRegister SourceRegister, bool KillSource,
35+
Register DestinationRegister,
36+
Register SourceRegister, bool KillSource,
3737
bool RenamableDest, bool RenamableSrc) const {
3838
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
3939
llvm_unreachable("Impossible reg-to-reg copy");

‎llvm/lib/Target/Lanai/LanaiInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,8 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
4848
int &FrameIndex) const override;
4949

5050
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
51-
const DebugLoc &DL, MCRegister DestinationRegister,
52-
MCRegister SourceRegister, bool KillSource,
51+
const DebugLoc &DL, Register DestinationRegister,
52+
Register SourceRegister, bool KillSource,
5353
bool RenamableDest = false,
5454
bool RenamableSrc = false) const override;
5555

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,8 @@ MCInst LoongArchInstrInfo::getNop() const {
3939

4040
void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4141
MachineBasicBlock::iterator MBBI,
42-
const DebugLoc &DL, MCRegister DstReg,
43-
MCRegister SrcReg, bool KillSrc,
42+
const DebugLoc &DL, Register DstReg,
43+
Register SrcReg, bool KillSrc,
4444
bool RenamableDest,
4545
bool RenamableSrc) const {
4646
if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
3030
MCInst getNop() const override;
3131

3232
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
33-
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
33+
const DebugLoc &DL, Register DstReg, Register SrcReg,
3434
bool KillSrc, bool RenamableDest = false,
3535
bool RenamableSrc = false) const override;
3636

‎llvm/lib/Target/M68k/M68kInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -705,8 +705,8 @@ bool M68kInstrInfo::isPCRelRegisterOperandLegal(
705705

706706
void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
707707
MachineBasicBlock::iterator MI,
708-
const DebugLoc &DL, MCRegister DstReg,
709-
MCRegister SrcReg, bool KillSrc,
708+
const DebugLoc &DL, Register DstReg,
709+
Register SrcReg, bool KillSrc,
710710
bool RenamableDest, bool RenamableSrc) const {
711711
unsigned Opc = 0;
712712

‎llvm/lib/Target/M68k/M68kInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -270,7 +270,7 @@ class M68kInstrInfo : public M68kGenInstrInfo {
270270
int *BytesAdded = nullptr) const override;
271271

272272
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
273-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
273+
const DebugLoc &DL, Register DestReg, Register SrcReg,
274274
bool KillSrc, bool RenamableDest = false,
275275
bool RenamableSrc = false) const override;
276276

‎llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,8 @@ void MSP430InstrInfo::loadRegFromStackSlot(
8383

8484
void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
8585
MachineBasicBlock::iterator I,
86-
const DebugLoc &DL, MCRegister DestReg,
87-
MCRegister SrcReg, bool KillSrc,
86+
const DebugLoc &DL, Register DestReg,
87+
Register SrcReg, bool KillSrc,
8888
bool RenamableDest, bool RenamableSrc) const {
8989
unsigned Opc;
9090
if (MSP430::GR16RegClass.contains(DestReg, SrcReg))

‎llvm/lib/Target/MSP430/MSP430InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
3636
const MSP430RegisterInfo &getRegisterInfo() const { return RI; }
3737

3838
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
39-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
39+
const DebugLoc &DL, Register DestReg, Register SrcReg,
4040
bool KillSrc, bool RenamableDest = false,
4141
bool RenamableSrc = false) const override;
4242

‎llvm/lib/Target/Mips/Mips16InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,8 @@ Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
6565

6666
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6767
MachineBasicBlock::iterator I,
68-
const DebugLoc &DL, MCRegister DestReg,
69-
MCRegister SrcReg, bool KillSrc,
68+
const DebugLoc &DL, Register DestReg,
69+
Register SrcReg, bool KillSrc,
7070
bool RenamableDest, bool RenamableSrc) const {
7171
unsigned Opc = 0;
7272

‎llvm/lib/Target/Mips/Mips16InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ class Mips16InstrInfo : public MipsInstrInfo {
4949
int &FrameIndex) const override;
5050

5151
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
52-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
52+
const DebugLoc &DL, Register DestReg, Register SrcReg,
5353
bool KillSrc, bool RenamableDest = false,
5454
bool RenamableSrc = false) const override;
5555

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