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[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions.
Most of the test changes are because we aren't consistent about what rounding mode to use for fcvt.s.bf16 instructions. See also llvm#106948.
1 parent 5bd3ee0 commit a99e613

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8 files changed

+94
-91
lines changed

8 files changed

+94
-91
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -462,6 +462,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
462462
setOperationAction(ISD::FABS, MVT::bf16, Custom);
463463
setOperationAction(ISD::FNEG, MVT::bf16, Custom);
464464
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
465+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
465466
}
466467

467468
if (Subtarget.hasStdExtZfhminOrZhinxmin()) {
@@ -480,6 +481,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
480481
setOperationAction(ISD::FABS, MVT::f16, Custom);
481482
setOperationAction(ISD::FNEG, MVT::f16, Custom);
482483
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
484+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
483485
}
484486

485487
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
@@ -592,9 +594,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
592594
setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
593595
Custom);
594596

597+
// f16/bf16 require custom handling.
595598
setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
596599
ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
597-
XLenVT, Legal);
600+
XLenVT, Custom);
598601

599602
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
600603
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
@@ -3068,6 +3071,30 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
30683071
return Res;
30693072
}
30703073

3074+
static SDValue lowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3075+
const RISCVSubtarget &Subtarget) {
3076+
bool IsStrict = Op->isStrictFPOpcode();
3077+
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
3078+
3079+
// f16 conversions are promoted to f32 when Zfh/Zhinx are no supported.
3080+
if ((SrcVal.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) ||
3081+
SrcVal.getValueType() == MVT::bf16) {
3082+
SDLoc DL(Op);
3083+
if (IsStrict) {
3084+
SDValue Ext =
3085+
DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
3086+
{Op.getOperand(0), SrcVal});
3087+
return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
3088+
{Ext.getValue(1), Ext.getValue(0)});
3089+
}
3090+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
3091+
DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, SrcVal));
3092+
}
3093+
3094+
// Other operations are legal.
3095+
return Op;
3096+
}
3097+
30713098
static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
30723099
switch (Opc) {
30733100
case ISD::FROUNDEVEN:
@@ -6582,6 +6609,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
65826609
// the source. We custom-lower any conversions that do two hops into
65836610
// sequences.
65846611
MVT VT = Op.getSimpleValueType();
6612+
if (VT.isScalarInteger())
6613+
return lowerFP_TO_INT(Op, DAG, Subtarget);
65856614
if (!VT.isVector())
65866615
return Op;
65876616
SDLoc DL(Op);

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -67,22 +67,12 @@ def : Pat<(riscv_fmv_x_signexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
6767
} // Predicates = [HasStdExtZfbfmin]
6868

6969
let Predicates = [HasStdExtZfbfmin] in {
70-
// bf16->[u]int. Round-to-zero must be used for the f32->int step, the
71-
// rounding mode has no effect for bf16->f32.
72-
def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
73-
def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
74-
7570
// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
7671
def : Pat<(bf16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
7772
def : Pat<(bf16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
7873
}
7974

8075
let Predicates = [HasStdExtZfbfmin, IsRV64] in {
81-
// bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
82-
// rounding mode has no effect for bf16->f32.
83-
def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
84-
def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
85-
8676
// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
8777
def : Pat<(bf16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
8878
def : Pat<(bf16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -601,40 +601,24 @@ def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H
601601
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]
602602

603603
let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
604-
// half->[u]int. Round-to-zero must be used.
605-
def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
606-
def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
607-
608604
// [u]int->half. Match GCC and default to using dynamic rounding mode.
609605
def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
610606
def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
611607
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]
612608

613609
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
614-
// half->[u]int. Round-to-zero must be used.
615-
def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
616-
def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
617-
618610
// [u]int->half. Match GCC and default to using dynamic rounding mode.
619611
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_W_INX $rs1, FRM_DYN), FRM_DYN)>;
620612
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_WU_INX $rs1, FRM_DYN), FRM_DYN)>;
621613
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx]
622614

623615
let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
624-
// half->[u]int64. Round-to-zero must be used.
625-
def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
626-
def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
627-
628616
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
629617
def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
630618
def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
631619
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
632620

633621
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
634-
// half->[u]int64. Round-to-zero must be used.
635-
def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
636-
def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
637-
638622
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
639623
def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_L_INX $rs1, FRM_DYN), FRM_DYN)>;
640624
def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_LU_INX $rs1, FRM_DYN), FRM_DYN)>;

‎llvm/test/CodeGen/RISCV/bfloat-convert.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
define i16 @fcvt_si_bf16(bfloat %a) nounwind {
1919
; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
2020
; CHECK32ZFBFMIN: # %bb.0:
21-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
21+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
2222
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
2323
; CHECK32ZFBFMIN-NEXT: ret
2424
;
@@ -32,7 +32,7 @@ define i16 @fcvt_si_bf16(bfloat %a) nounwind {
3232
;
3333
; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
3434
; CHECK64ZFBFMIN: # %bb.0:
35-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
35+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
3636
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
3737
; CHECK64ZFBFMIN-NEXT: ret
3838
;
@@ -120,8 +120,8 @@ declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
120120
define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
121121
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
122122
; CHECK32ZFBFMIN: # %bb.0:
123-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
124-
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
123+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
124+
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
125125
; CHECK32ZFBFMIN-NEXT: ret
126126
;
127127
; RV32ID-LABEL: fcvt_ui_bf16:
@@ -134,8 +134,8 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
134134
;
135135
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
136136
; CHECK64ZFBFMIN: # %bb.0:
137-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
138-
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
137+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
138+
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
139139
; CHECK64ZFBFMIN-NEXT: ret
140140
;
141141
; RV64ID-LABEL: fcvt_ui_bf16:
@@ -206,7 +206,7 @@ declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
206206
define i32 @fcvt_w_bf16(bfloat %a) nounwind {
207207
; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
208208
; CHECK32ZFBFMIN: # %bb.0:
209-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
209+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
210210
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
211211
; CHECK32ZFBFMIN-NEXT: ret
212212
;
@@ -288,7 +288,7 @@ declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
288288
define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
289289
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
290290
; CHECK32ZFBFMIN: # %bb.0:
291-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
291+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
292292
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
293293
; CHECK32ZFBFMIN-NEXT: ret
294294
;
@@ -320,7 +320,7 @@ define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
320320
define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
321321
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
322322
; CHECK32ZFBFMIN: # %bb.0:
323-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
323+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
324324
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
325325
; CHECK32ZFBFMIN-NEXT: seqz a1, a0
326326
; CHECK32ZFBFMIN-NEXT: add a0, a0, a1
@@ -438,7 +438,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind {
438438
;
439439
; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
440440
; CHECK64ZFBFMIN: # %bb.0:
441-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
441+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
442442
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
443443
; CHECK64ZFBFMIN-NEXT: ret
444444
;
@@ -625,7 +625,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
625625
;
626626
; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
627627
; CHECK64ZFBFMIN: # %bb.0:
628-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
628+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
629629
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
630630
; CHECK64ZFBFMIN-NEXT: ret
631631
;
@@ -1470,7 +1470,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind
14701470
define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
14711471
; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
14721472
; CHECK32ZFBFMIN: # %bb.0:
1473-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1473+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
14741474
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
14751475
; CHECK32ZFBFMIN-NEXT: ret
14761476
;
@@ -1484,7 +1484,7 @@ define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
14841484
;
14851485
; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
14861486
; CHECK64ZFBFMIN: # %bb.0:
1487-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1487+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
14881488
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
14891489
; CHECK64ZFBFMIN-NEXT: ret
14901490
;
@@ -1572,8 +1572,8 @@ declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
15721572
define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
15731573
; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
15741574
; CHECK32ZFBFMIN: # %bb.0:
1575-
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1576-
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1575+
; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1576+
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
15771577
; CHECK32ZFBFMIN-NEXT: ret
15781578
;
15791579
; RV32ID-LABEL: fcvt_wu_s_i8:
@@ -1586,7 +1586,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
15861586
;
15871587
; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
15881588
; CHECK64ZFBFMIN: # %bb.0:
1589-
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1589+
; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
15901590
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
15911591
; CHECK64ZFBFMIN-NEXT: ret
15921592
;

‎llvm/test/CodeGen/RISCV/half-convert-strict.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -136,78 +136,78 @@ declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
136136
define i16 @fcvt_ui_h(half %a) nounwind strictfp {
137137
; RV32IZFH-LABEL: fcvt_ui_h:
138138
; RV32IZFH: # %bb.0:
139-
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
139+
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
140140
; RV32IZFH-NEXT: ret
141141
;
142142
; RV64IZFH-LABEL: fcvt_ui_h:
143143
; RV64IZFH: # %bb.0:
144-
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
144+
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
145145
; RV64IZFH-NEXT: ret
146146
;
147147
; RV32IZHINX-LABEL: fcvt_ui_h:
148148
; RV32IZHINX: # %bb.0:
149-
; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
149+
; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
150150
; RV32IZHINX-NEXT: ret
151151
;
152152
; RV64IZHINX-LABEL: fcvt_ui_h:
153153
; RV64IZHINX: # %bb.0:
154-
; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
154+
; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
155155
; RV64IZHINX-NEXT: ret
156156
;
157157
; RV32IDZFH-LABEL: fcvt_ui_h:
158158
; RV32IDZFH: # %bb.0:
159-
; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
159+
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
160160
; RV32IDZFH-NEXT: ret
161161
;
162162
; RV64IDZFH-LABEL: fcvt_ui_h:
163163
; RV64IDZFH: # %bb.0:
164-
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
164+
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
165165
; RV64IDZFH-NEXT: ret
166166
;
167167
; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
168168
; RV32IZDINXZHINX: # %bb.0:
169-
; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
169+
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
170170
; RV32IZDINXZHINX-NEXT: ret
171171
;
172172
; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
173173
; RV64IZDINXZHINX: # %bb.0:
174-
; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
174+
; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
175175
; RV64IZDINXZHINX-NEXT: ret
176176
;
177177
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
178178
; CHECK32-IZFHMIN: # %bb.0:
179179
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
180-
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
180+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
181181
; CHECK32-IZFHMIN-NEXT: ret
182182
;
183183
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
184184
; CHECK64-IZFHMIN: # %bb.0:
185185
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
186-
; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
186+
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
187187
; CHECK64-IZFHMIN-NEXT: ret
188188
;
189189
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
190190
; CHECK32-IZHINXMIN: # %bb.0:
191191
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
192-
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
192+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
193193
; CHECK32-IZHINXMIN-NEXT: ret
194194
;
195195
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
196196
; CHECK64-IZHINXMIN: # %bb.0:
197197
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
198-
; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
198+
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
199199
; CHECK64-IZHINXMIN-NEXT: ret
200200
;
201201
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
202202
; CHECK32-IZDINXZHINXMIN: # %bb.0:
203203
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
204-
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
204+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
205205
; CHECK32-IZDINXZHINXMIN-NEXT: ret
206206
;
207207
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
208208
; CHECK64-IZDINXZHINXMIN: # %bb.0:
209209
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
210-
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
210+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
211211
; CHECK64-IZDINXZHINXMIN-NEXT: ret
212212
%1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict")
213213
ret i16 %1

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