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[GlobalIsel][AArch64] Select G_SCMP and G_UCMP
llvm#91871 llvm#98774
1 parent 233cca1 commit 2baded3

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7 files changed

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-60
lines changed

7 files changed

+322
-60
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -900,6 +900,25 @@ class GShl : public GenericMachineInstr {
900900
};
901901
};
902902

903+
/// Represents a threeway compare.
904+
class GSUCmp : public GenericMachineInstr {
905+
public:
906+
Register getLHSReg() const { return getOperand(1).getReg(); }
907+
Register getRHSReg() const { return getOperand(2).getReg(); }
908+
909+
bool isSigned() const { return getOpcode() == TargetOpcode::G_SCMP; }
910+
911+
static bool classof(const MachineInstr *MI) {
912+
switch (MI->getOpcode()) {
913+
case TargetOpcode::G_SCMP:
914+
case TargetOpcode::G_UCMP:
915+
return true;
916+
default:
917+
return false;
918+
}
919+
};
920+
};
921+
903922
} // namespace llvm
904923

905924
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,7 @@ class LegalizerHelper {
402402

403403
LegalizeResult lowerISFPCLASS(MachineInstr &MI);
404404

405+
LegalizeResult lowerThreewayCompare(MachineInstr &MI);
405406
LegalizeResult lowerMinMax(MachineInstr &MI);
406407
LegalizeResult lowerFCopySign(MachineInstr &MI);
407408
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4006,6 +4006,9 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
40064006
case G_UMIN:
40074007
case G_UMAX:
40084008
return lowerMinMax(MI);
4009+
case G_SCMP:
4010+
case G_UCMP:
4011+
return lowerThreewayCompare(MI);
40094012
case G_FCOPYSIGN:
40104013
return lowerFCopySign(MI);
40114014
case G_FMINNUM:
@@ -7269,6 +7272,36 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
72697272
return Legalized;
72707273
}
72717274

7275+
LegalizerHelper::LegalizeResult
7276+
LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
7277+
GSUCmp *Cmp = cast<GSUCmp>(&MI);
7278+
7279+
Register Dst = Cmp->getReg(0);
7280+
LLT DstTy = MRI.getType(Dst);
7281+
LLT CmpTy = DstTy.changeElementSize(1);
7282+
7283+
CmpInst::Predicate LTPredicate = Cmp->isSigned()
7284+
? CmpInst::Predicate::ICMP_SLT
7285+
: CmpInst::Predicate::ICMP_ULT;
7286+
CmpInst::Predicate GTPredicate = Cmp->isSigned()
7287+
? CmpInst::Predicate::ICMP_SGT
7288+
: CmpInst::Predicate::ICMP_UGT;
7289+
7290+
auto One = MIRBuilder.buildConstant(DstTy, 1);
7291+
auto Zero = MIRBuilder.buildConstant(DstTy, 0);
7292+
auto MinusOne = MIRBuilder.buildConstant(DstTy, -1);
7293+
7294+
auto IsLT = MIRBuilder.buildICmp(LTPredicate, CmpTy, Cmp->getLHSReg(),
7295+
Cmp->getRHSReg());
7296+
auto IsGT = MIRBuilder.buildICmp(GTPredicate, CmpTy, Cmp->getLHSReg(),
7297+
Cmp->getRHSReg());
7298+
auto SelectZeroOrOne = MIRBuilder.buildSelect(DstTy, IsGT, One, Zero);
7299+
MIRBuilder.buildSelect(Dst, IsLT, MinusOne, SelectZeroOrOne);
7300+
7301+
MI.eraseFromParent();
7302+
return Legalized;
7303+
}
7304+
72727305
LegalizerHelper::LegalizeResult
72737306
LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
72747307
auto [Dst, DstTy, Src0, Src0Ty, Src1, Src1Ty] = MI.getFirst3RegLLTs();

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1288,6 +1288,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
12881288

12891289
getActionDefinitionsBuilder(G_PREFETCH).custom();
12901290

1291+
getActionDefinitionsBuilder({G_SCMP, G_UCMP}).lower();
1292+
12911293
getLegacyLegalizerInfo().computeTables();
12921294
verify(*ST.getInstrInfo());
12931295
}

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-threeway-cmp.mir

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,109 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3+
---
4+
name: test_scmp
5+
body: |
6+
bb.0.entry:
7+
; CHECK-LABEL: name: test_scmp
8+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
10+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
11+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s64), [[COPY1]]
12+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
13+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[C]], [[C1]]
15+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
16+
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C2]], [[SELECT]]
17+
; CHECK-NEXT: $w0 = COPY [[SELECT1]](s32)
18+
%0:_(s64) = COPY $x0
19+
%1:_(s64) = COPY $x0
20+
%4:_(s2) = G_SCMP %0(s64), %1
21+
%14:_(s32) = G_ANYEXT %4(s2)
22+
$w0 = COPY %14(s32)
23+
24+
...
25+
---
26+
name: test_ucmp
27+
body: |
28+
bb.0.entry:
29+
; CHECK-LABEL: name: test_ucmp
30+
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
31+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
32+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
33+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s64), [[COPY1]]
34+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
35+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
36+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[C]], [[C1]]
37+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
38+
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C2]], [[SELECT]]
39+
; CHECK-NEXT: $w0 = COPY [[SELECT1]](s32)
40+
%0:_(s64) = COPY $x0
41+
%1:_(s64) = COPY $x0
42+
%4:_(s2) = G_UCMP %0(s64), %1
43+
%14:_(s32) = G_ANYEXT %4(s2)
44+
$w0 = COPY %14(s32)
45+
46+
...
47+
---
48+
name: test_ucmp_vector
49+
body: |
50+
bb.0.entry:
51+
; CHECK-LABEL: name: test_ucmp_vector
52+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
53+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
54+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
55+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
56+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
57+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $w0
58+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $w1
59+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $w2
60+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $w3
61+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
62+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
63+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
64+
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
65+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
66+
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[BUILD_VECTOR]](<4 x s32>), [[BUILD_VECTOR1]]
67+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
68+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
69+
; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
70+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR2]](<8 x s8>)
71+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT]](<8 x s16>)
72+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[TRUNC]], [[UV]]
73+
; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
74+
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR3]](<8 x s8>)
75+
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT1]](<8 x s16>)
76+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
77+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[UV2]], [[TRUNC1]]
78+
; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
79+
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR4]](<8 x s8>)
80+
; CHECK-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT2]](<8 x s16>)
81+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[UV4]], [[XOR]]
82+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[AND]], [[AND1]]
83+
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
84+
; CHECK-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
85+
; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR5]](<8 x s8>)
86+
; CHECK-NEXT: [[UV6:%[0-9]+]]:_(<4 x s16>), [[UV7:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT3]](<8 x s16>)
87+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<4 x s16>) = G_XOR [[TRUNC2]], [[UV6]]
88+
; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
89+
; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[BUILD_VECTOR6]](<8 x s8>)
90+
; CHECK-NEXT: [[UV8:%[0-9]+]]:_(<4 x s16>), [[UV9:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[ANYEXT4]](<8 x s16>)
91+
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
92+
; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<4 x s16>) = G_AND [[UV8]], [[TRUNC3]]
93+
; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<4 x s16>) = G_AND [[OR]], [[XOR1]]
94+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<4 x s16>) = G_OR [[AND2]], [[AND3]]
95+
; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[OR1]](<4 x s16>)
96+
; CHECK-NEXT: $q0 = COPY [[ANYEXT5]](<4 x s32>)
97+
%0:_(s32) = COPY $w0
98+
%1:_(s32) = COPY $w1
99+
%2:_(s32) = COPY $w2
100+
%3:_(s32) = COPY $w3
101+
%4:_(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
102+
%5:_(s32) = COPY $w0
103+
%6:_(s32) = COPY $w1
104+
%7:_(s32) = COPY $w2
105+
%8:_(s32) = COPY $w3
106+
%9:_(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)
107+
%10:_(<4 x s2>) = G_UCMP %4(<4 x s32>), %9
108+
%11:_(<4 x s32>) = G_ANYEXT %10(<4 x s2>)
109+
$q0 = COPY %11(<4 x s32>)

‎llvm/test/CodeGen/AArch64/scmp.ll

Lines changed: 62 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,45 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2-
; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
34

45
define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {
5-
; CHECK-LABEL: scmp.8.8:
6-
; CHECK: // %bb.0:
7-
; CHECK-NEXT: sxtb w8, w0
8-
; CHECK-NEXT: cmp w8, w1, sxtb
9-
; CHECK-NEXT: cset w8, gt
10-
; CHECK-NEXT: csinv w0, w8, wzr, ge
11-
; CHECK-NEXT: ret
6+
; CHECK-SD-LABEL: scmp.8.8:
7+
; CHECK-SD: // %bb.0:
8+
; CHECK-SD-NEXT: sxtb w8, w0
9+
; CHECK-SD-NEXT: cmp w8, w1, sxtb
10+
; CHECK-SD-NEXT: cset w8, gt
11+
; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
12+
; CHECK-SD-NEXT: ret
13+
;
14+
; CHECK-GI-LABEL: scmp.8.8:
15+
; CHECK-GI: // %bb.0:
16+
; CHECK-GI-NEXT: sxtb w8, w0
17+
; CHECK-GI-NEXT: sxtb w9, w1
18+
; CHECK-GI-NEXT: cmp w8, w9
19+
; CHECK-GI-NEXT: cset w8, gt
20+
; CHECK-GI-NEXT: csinv w0, w8, wzr, ge
21+
; CHECK-GI-NEXT: ret
1222
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
1323
ret i8 %1
1424
}
1525

1626
define i8 @scmp.8.16(i16 %x, i16 %y) nounwind {
17-
; CHECK-LABEL: scmp.8.16:
18-
; CHECK: // %bb.0:
19-
; CHECK-NEXT: sxth w8, w0
20-
; CHECK-NEXT: cmp w8, w1, sxth
21-
; CHECK-NEXT: cset w8, gt
22-
; CHECK-NEXT: csinv w0, w8, wzr, ge
23-
; CHECK-NEXT: ret
27+
; CHECK-SD-LABEL: scmp.8.16:
28+
; CHECK-SD: // %bb.0:
29+
; CHECK-SD-NEXT: sxth w8, w0
30+
; CHECK-SD-NEXT: cmp w8, w1, sxth
31+
; CHECK-SD-NEXT: cset w8, gt
32+
; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
33+
; CHECK-SD-NEXT: ret
34+
;
35+
; CHECK-GI-LABEL: scmp.8.16:
36+
; CHECK-GI: // %bb.0:
37+
; CHECK-GI-NEXT: sxth w8, w0
38+
; CHECK-GI-NEXT: sxth w9, w1
39+
; CHECK-GI-NEXT: cmp w8, w9
40+
; CHECK-GI-NEXT: cset w8, gt
41+
; CHECK-GI-NEXT: csinv w0, w8, wzr, ge
42+
; CHECK-GI-NEXT: ret
2443
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
2544
ret i8 %1
2645
}
@@ -48,15 +67,34 @@ define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
4867
}
4968

5069
define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
51-
; CHECK-LABEL: scmp.8.128:
52-
; CHECK: // %bb.0:
53-
; CHECK-NEXT: cmp x2, x0
54-
; CHECK-NEXT: sbcs xzr, x3, x1
55-
; CHECK-NEXT: cset w8, lt
56-
; CHECK-NEXT: cmp x0, x2
57-
; CHECK-NEXT: sbcs xzr, x1, x3
58-
; CHECK-NEXT: csinv w0, w8, wzr, ge
59-
; CHECK-NEXT: ret
70+
; CHECK-SD-LABEL: scmp.8.128:
71+
; CHECK-SD: // %bb.0:
72+
; CHECK-SD-NEXT: cmp x2, x0
73+
; CHECK-SD-NEXT: sbcs xzr, x3, x1
74+
; CHECK-SD-NEXT: cset w8, lt
75+
; CHECK-SD-NEXT: cmp x0, x2
76+
; CHECK-SD-NEXT: sbcs xzr, x1, x3
77+
; CHECK-SD-NEXT: csinv w0, w8, wzr, ge
78+
; CHECK-SD-NEXT: ret
79+
;
80+
; CHECK-GI-LABEL: scmp.8.128:
81+
; CHECK-GI: // %bb.0:
82+
; CHECK-GI-NEXT: cmp x1, x3
83+
; CHECK-GI-NEXT: cset w8, lt
84+
; CHECK-GI-NEXT: cmp x0, x2
85+
; CHECK-GI-NEXT: cset w9, lo
86+
; CHECK-GI-NEXT: cmp x1, x3
87+
; CHECK-GI-NEXT: csel w8, w9, w8, eq
88+
; CHECK-GI-NEXT: cset w9, gt
89+
; CHECK-GI-NEXT: cmp x0, x2
90+
; CHECK-GI-NEXT: cset w10, hi
91+
; CHECK-GI-NEXT: cmp x1, x3
92+
; CHECK-GI-NEXT: csel w9, w10, w9, eq
93+
; CHECK-GI-NEXT: tst w9, #0x1
94+
; CHECK-GI-NEXT: cset w9, ne
95+
; CHECK-GI-NEXT: tst w8, #0x1
96+
; CHECK-GI-NEXT: csinv w0, w9, wzr, eq
97+
; CHECK-GI-NEXT: ret
6098
%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
6199
ret i8 %1
62100
}

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