|
8 | 8 | * Author: Hezi Shahmoon <[email protected]>
|
9 | 9 | */
|
10 | 10 |
|
| 11 | +#include <linux/bitfield.h> |
11 | 12 | #include <linux/delay.h>
|
12 | 13 | #include <linux/gpio/consumer.h>
|
13 | 14 | #include <linux/interrupt.h>
|
@@ -858,14 +859,11 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
|
858 | 859 |
|
859 | 860 |
|
860 | 861 | switch (reg) {
|
861 |
| - case PCI_EXP_SLTCTL: |
862 |
| - *value = PCI_EXP_SLTSTA_PDS << 16; |
863 |
| - return PCI_BRIDGE_EMUL_HANDLED; |
864 |
| - |
865 | 862 | /*
|
866 |
| - * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need |
867 |
| - * to be handled here, because their values are stored in emulated |
868 |
| - * config space buffer, and we read them from there when needed. |
| 863 | + * PCI_EXP_SLTCAP, PCI_EXP_SLTCTL, PCI_EXP_RTCTL and PCI_EXP_RTSTA are |
| 864 | + * also supported, but do not need to be handled here, because their |
| 865 | + * values are stored in emulated config space buffer, and we read them |
| 866 | + * from there when needed. |
869 | 867 | */
|
870 | 868 |
|
871 | 869 | case PCI_EXP_LNKCAP: {
|
@@ -1056,8 +1054,25 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
|
1056 | 1054 | /* Support interrupt A for MSI feature */
|
1057 | 1055 | bridge->conf.intpin = PCI_INTERRUPT_INTA;
|
1058 | 1056 |
|
1059 |
| - /* Aardvark HW provides PCIe Capability structure in version 2 */ |
1060 |
| - bridge->pcie_conf.cap = cpu_to_le16(2); |
| 1057 | + /* |
| 1058 | + * Aardvark HW provides PCIe Capability structure in version 2 and |
| 1059 | + * indicate slot support, which is emulated. |
| 1060 | + */ |
| 1061 | + bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); |
| 1062 | + |
| 1063 | + /* |
| 1064 | + * Set Presence Detect State bit permanently since there is no support |
| 1065 | + * for unplugging the card nor detecting whether it is plugged. (If a |
| 1066 | + * platform exists in the future that supports it, via a GPIO for |
| 1067 | + * example, it should be implemented via this bit.) |
| 1068 | + * |
| 1069 | + * Set physical slot number to 1 since there is only one port and zero |
| 1070 | + * value is reserved for ports within the same silicon as Root Port |
| 1071 | + * which is not our case. |
| 1072 | + */ |
| 1073 | + bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, |
| 1074 | + 1)); |
| 1075 | + bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); |
1061 | 1076 |
|
1062 | 1077 | /* Indicates supports for Completion Retry Status */
|
1063 | 1078 | bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
|
|
0 commit comments