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Alex Elderkuba-moo
Alex Elder
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kuba-moo
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net: ipa: add IPA v5.0 GSI register definitions
Add the definitions of GSI register offsets and fields for IPA v5.0. These are used for the SDX65 SoC. Increase the maximum channel and event ring counts supported by the driver, so those implemented by the SDX65 are supported. Signed-off-by: Alex Elder <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
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-3
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5 files changed

+324
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lines changed

‎drivers/net/ipa/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
IPA_REG_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11 5.0
66

77
# Some IPA versions can reuse another set of GSI register definitions.
8-
GSI_REG_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11
8+
GSI_REG_VERSIONS := 3.1 3.5.1 4.0 4.5 4.9 4.11 5.0
99

1010
IPA_DATA_VERSIONS := 3.1 3.5.1 4.2 4.5 4.7 4.9 4.11
1111

‎drivers/net/ipa/gsi.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@
1616
#include "ipa_version.h"
1717

1818
/* Maximum number of channels and event rings supported by the driver */
19-
#define GSI_CHANNEL_COUNT_MAX 23
20-
#define GSI_EVT_RING_COUNT_MAX 24
19+
#define GSI_CHANNEL_COUNT_MAX 28
20+
#define GSI_EVT_RING_COUNT_MAX 28
2121

2222
/* Maximum TLV FIFO size for a channel; 64 here is arbitrary (and high) */
2323
#define GSI_TLV_MAX 64

‎drivers/net/ipa/gsi_reg.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,9 @@ static const struct regs *gsi_regs(struct gsi *gsi)
109109
case IPA_VERSION_4_11:
110110
return &gsi_regs_v4_11;
111111

112+
case IPA_VERSION_5_0:
113+
return &gsi_regs_v5_0;
114+
112115
default:
113116
return NULL;
114117
}

‎drivers/net/ipa/gsi_reg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -355,6 +355,7 @@ extern const struct regs gsi_regs_v4_0;
355355
extern const struct regs gsi_regs_v4_5;
356356
extern const struct regs gsi_regs_v4_9;
357357
extern const struct regs gsi_regs_v4_11;
358+
extern const struct regs gsi_regs_v5_0;
358359

359360
/**
360361
* gsi_reg() - Return the structure describing a GSI register

‎drivers/net/ipa/reg/gsi_reg-v5.0.c

Lines changed: 317 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,317 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
3+
/* Copyright (C) 2023 Linaro Ltd. */
4+
5+
#include <linux/types.h>
6+
7+
#include "../gsi.h"
8+
#include "../reg.h"
9+
#include "../gsi_reg.h"
10+
11+
REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12+
0x0000c01c + 0x1000 * GSI_EE_AP);
13+
14+
REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15+
0x0000c028 + 0x1000 * GSI_EE_AP);
16+
17+
static const u32 reg_ch_c_cntxt_0_fmask[] = {
18+
[CHTYPE_PROTOCOL] = GENMASK(6, 0),
19+
[CHTYPE_DIR] = BIT(7),
20+
[CH_EE] = GENMASK(11, 8),
21+
[CHID] = GENMASK(19, 12),
22+
[CHSTATE] = GENMASK(23, 20),
23+
[ELEMENT_SIZE] = GENMASK(31, 24),
24+
};
25+
26+
REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
27+
0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
28+
29+
static const u32 reg_ch_c_cntxt_1_fmask[] = {
30+
[CH_R_LENGTH] = GENMASK(23, 0),
31+
[ERINDEX] = GENMASK(31, 24),
32+
};
33+
34+
REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
35+
0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
36+
37+
REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
38+
39+
REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
40+
41+
static const u32 reg_ch_c_qos_fmask[] = {
42+
[WRR_WEIGHT] = GENMASK(3, 0),
43+
/* Bits 4-7 reserved */
44+
[MAX_PREFETCH] = BIT(8),
45+
[USE_DB_ENG] = BIT(9),
46+
[PREFETCH_MODE] = GENMASK(13, 10),
47+
/* Bits 14-15 reserved */
48+
[EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
49+
[DB_IN_BYTES] = BIT(24),
50+
[LOW_LATENCY_EN] = BIT(25),
51+
/* Bits 26-31 reserved */
52+
};
53+
54+
REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
55+
56+
REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
57+
0x0001404c + 0x12000 * GSI_EE_AP, 0x80);
58+
59+
REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
60+
0x00014050 + 0x12000 * GSI_EE_AP, 0x80);
61+
62+
REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
63+
0x00014054 + 0x12000 * GSI_EE_AP, 0x80);
64+
65+
REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
66+
0x00014058 + 0x12000 * GSI_EE_AP, 0x80);
67+
68+
static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
69+
[EV_CHTYPE] = GENMASK(6, 0),
70+
[EV_INTYPE] = BIT(7),
71+
[EV_EVCHID] = GENMASK(15, 8),
72+
[EV_EE] = GENMASK(19, 16),
73+
[EV_CHSTATE] = GENMASK(23, 20),
74+
[EV_ELEMENT_SIZE] = GENMASK(31, 24),
75+
};
76+
77+
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
78+
0x0001c000 + 0x12000 * GSI_EE_AP, 0x80);
79+
80+
static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
81+
[R_LENGTH] = GENMASK(19, 0),
82+
};
83+
84+
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
85+
0x0001c004 + 0x12000 * GSI_EE_AP, 0x80);
86+
87+
REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
88+
0x0001c008 + 0x12000 * GSI_EE_AP, 0x80);
89+
90+
REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
91+
0x0001c00c + 0x12000 * GSI_EE_AP, 0x80);
92+
93+
REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
94+
0x0001c010 + 0x12000 * GSI_EE_AP, 0x80);
95+
96+
static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
97+
[EV_MODT] = GENMASK(15, 0),
98+
[EV_MODC] = GENMASK(23, 16),
99+
[EV_MOD_CNT] = GENMASK(31, 24),
100+
};
101+
102+
REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
103+
0x0001c020 + 0x12000 * GSI_EE_AP, 0x80);
104+
105+
REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
106+
0x0001c024 + 0x12000 * GSI_EE_AP, 0x80);
107+
108+
REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
109+
0x0001c028 + 0x12000 * GSI_EE_AP, 0x80);
110+
111+
REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
112+
0x0001c02c + 0x12000 * GSI_EE_AP, 0x80);
113+
114+
REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
115+
0x0001c030 + 0x12000 * GSI_EE_AP, 0x80);
116+
117+
REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
118+
0x0001c034 + 0x12000 * GSI_EE_AP, 0x80);
119+
120+
REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
121+
0x0001c048 + 0x12000 * GSI_EE_AP, 0x80);
122+
123+
REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
124+
0x0001c04c + 0x12000 * GSI_EE_AP, 0x80);
125+
126+
REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
127+
0x00024000 + 0x12000 * GSI_EE_AP, 0x08);
128+
129+
REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
130+
0x00024800 + 0x12000 * GSI_EE_AP, 0x08);
131+
132+
static const u32 reg_gsi_status_fmask[] = {
133+
[ENABLED] = BIT(0),
134+
/* Bits 1-31 reserved */
135+
};
136+
137+
REG_FIELDS(GSI_STATUS, gsi_status, 0x00025000 + 0x12000 * GSI_EE_AP);
138+
139+
static const u32 reg_ch_cmd_fmask[] = {
140+
[CH_CHID] = GENMASK(7, 0),
141+
/* Bits 8-23 reserved */
142+
[CH_OPCODE] = GENMASK(31, 24),
143+
};
144+
145+
REG_FIELDS(CH_CMD, ch_cmd, 0x00025008 + 0x12000 * GSI_EE_AP);
146+
147+
static const u32 reg_ev_ch_cmd_fmask[] = {
148+
[EV_CHID] = GENMASK(7, 0),
149+
/* Bits 8-23 reserved */
150+
[EV_OPCODE] = GENMASK(31, 24),
151+
};
152+
153+
REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00025010 + 0x12000 * GSI_EE_AP);
154+
155+
static const u32 reg_generic_cmd_fmask[] = {
156+
[GENERIC_OPCODE] = GENMASK(4, 0),
157+
[GENERIC_CHID] = GENMASK(9, 5),
158+
[GENERIC_EE] = GENMASK(13, 10),
159+
/* Bits 14-31 reserved */
160+
};
161+
162+
REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00025018 + 0x12000 * GSI_EE_AP);
163+
164+
static const u32 reg_hw_param_2_fmask[] = {
165+
[NUM_CH_PER_EE] = GENMASK(7, 0),
166+
[IRAM_SIZE] = GENMASK(12, 8),
167+
[GSI_CH_PEND_TRANSLATE] = BIT(13),
168+
[GSI_CH_FULL_LOGIC] = BIT(14),
169+
[GSI_USE_SDMA] = BIT(15),
170+
[GSI_SDMA_N_INT] = GENMASK(18, 16),
171+
[GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
172+
[GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
173+
[GSI_USE_RD_WR_ENG] = BIT(30),
174+
[GSI_USE_INTER_EE] = BIT(31),
175+
};
176+
177+
REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00025040 + 0x12000 * GSI_EE_AP);
178+
179+
static const u32 reg_hw_param_4_fmask[] = {
180+
[EV_PER_EE] = GENMASK(7, 0),
181+
[IRAM_PROTOCOL_COUNT] = GENMASK(15, 8),
182+
/* Bits 16-31 reserved */
183+
};
184+
185+
REG_FIELDS(HW_PARAM_4, hw_param_4, 0x00025050 + 0x12000 * GSI_EE_AP);
186+
187+
REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP);
188+
189+
REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP);
190+
191+
REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP);
192+
193+
REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
194+
0x00025094 + 0x12000 * GSI_EE_AP);
195+
196+
REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
197+
0x00025098 + 0x12000 * GSI_EE_AP);
198+
199+
REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP);
200+
201+
REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
202+
0x000250a0 + 0x12000 * GSI_EE_AP);
203+
204+
REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
205+
0x000250a4 + 0x12000 * GSI_EE_AP);
206+
207+
REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000250a8 + 0x12000 * GSI_EE_AP);
208+
209+
REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
210+
0x000250ac + 0x12000 * GSI_EE_AP);
211+
212+
REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
213+
0x000250b0 + 0x12000 * GSI_EE_AP);
214+
215+
REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00025200 + 0x12000 * GSI_EE_AP);
216+
217+
REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00025204 + 0x12000 * GSI_EE_AP);
218+
219+
REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00025208 + 0x12000 * GSI_EE_AP);
220+
221+
REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0002520c + 0x12000 * GSI_EE_AP);
222+
223+
REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00025210 + 0x12000 * GSI_EE_AP);
224+
225+
REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00025214 + 0x12000 * GSI_EE_AP);
226+
227+
static const u32 reg_cntxt_intset_fmask[] = {
228+
[INTYPE] = BIT(0)
229+
/* Bits 1-31 reserved */
230+
};
231+
232+
REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00025220 + 0x12000 * GSI_EE_AP);
233+
234+
static const u32 reg_error_log_fmask[] = {
235+
[ERR_ARG3] = GENMASK(3, 0),
236+
[ERR_ARG2] = GENMASK(7, 4),
237+
[ERR_ARG1] = GENMASK(11, 8),
238+
[ERR_CODE] = GENMASK(15, 12),
239+
/* Bits 16-18 reserved */
240+
[ERR_VIRT_IDX] = GENMASK(23, 19),
241+
[ERR_TYPE] = GENMASK(27, 24),
242+
[ERR_EE] = GENMASK(31, 28),
243+
};
244+
245+
REG_FIELDS(ERROR_LOG, error_log, 0x00025240 + 0x12000 * GSI_EE_AP);
246+
247+
REG(ERROR_LOG_CLR, error_log_clr, 0x00025244 + 0x12000 * GSI_EE_AP);
248+
249+
static const u32 reg_cntxt_scratch_0_fmask[] = {
250+
[INTER_EE_RESULT] = GENMASK(2, 0),
251+
/* Bits 3-4 reserved */
252+
[GENERIC_EE_RESULT] = GENMASK(7, 5),
253+
/* Bits 8-31 reserved */
254+
};
255+
256+
REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00025400 + 0x12000 * GSI_EE_AP);
257+
258+
static const struct reg *reg_array[] = {
259+
[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
260+
[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
261+
[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
262+
[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
263+
[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
264+
[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
265+
[CH_C_QOS] = &reg_ch_c_qos,
266+
[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
267+
[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
268+
[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
269+
[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
270+
[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
271+
[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
272+
[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
273+
[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
274+
[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
275+
[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
276+
[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
277+
[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
278+
[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
279+
[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
280+
[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
281+
[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
282+
[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
283+
[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
284+
[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
285+
[GSI_STATUS] = &reg_gsi_status,
286+
[CH_CMD] = &reg_ch_cmd,
287+
[EV_CH_CMD] = &reg_ev_ch_cmd,
288+
[GENERIC_CMD] = &reg_generic_cmd,
289+
[HW_PARAM_2] = &reg_hw_param_2,
290+
[HW_PARAM_4] = &reg_hw_param_4,
291+
[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
292+
[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
293+
[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
294+
[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
295+
[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
296+
[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
297+
[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
298+
[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
299+
[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
300+
[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
301+
[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
302+
[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
303+
[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
304+
[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
305+
[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
306+
[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
307+
[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
308+
[CNTXT_INTSET] = &reg_cntxt_intset,
309+
[ERROR_LOG] = &reg_error_log,
310+
[ERROR_LOG_CLR] = &reg_error_log_clr,
311+
[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
312+
};
313+
314+
const struct regs gsi_regs_v5_0 = {
315+
.reg_count = ARRAY_SIZE(reg_array),
316+
.reg = reg_array,
317+
};

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