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[SPARC] Mark the %g0 register as constant & use it to materialize zeros
Materialize zeros by copying from %g0, which is now marked as constant. This makes it possible for some common operations (like integer negation) to be performed in fewer instructions. This continues @arichardson's patch at D132561. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138887
1 parent d38d606 commit eaade37

17 files changed

+289
-292
lines changed

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,10 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;
6060

6161
// Single-instruction patterns.
6262

63+
// Zero immediate.
64+
def : Pat<(i64 0), (COPY (i64 G0))>,
65+
Requires<[Is64Bit]>;
66+
6367
// The ALU instructions want their simm13 operands as i32 immediates.
6468
def as_i32imm : SDNodeXForm<imm, [{
6569
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);

‎llvm/lib/Target/Sparc/SparcInstrInfo.td

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1782,8 +1782,7 @@ let Predicates = [HasV9] in {
17821782
//===----------------------------------------------------------------------===//
17831783

17841784
// Zero immediate.
1785-
def : Pat<(i32 0),
1786-
(ORrr (i32 G0), (i32 G0))>;
1785+
def : Pat<(i32 0), (COPY (i32 G0))>;
17871786
// Small immediates.
17881787
def : Pat<(i32 simm13:$val),
17891788
(ORri (i32 G0), imm:$val)>;
@@ -1864,6 +1863,16 @@ def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
18641863
def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
18651864
def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
18661865

1866+
// A register pair with zero upper half.
1867+
// The upper part is done with ORrr instead of `COPY G0`
1868+
// or a normal register copy, since `COPY G0`s in that place
1869+
// will be converted into `COPY G0_G1` later on, which is not
1870+
// what we want in this case.
1871+
def : Pat<(build_vector (i32 0), (i32 IntRegs:$a2)),
1872+
(INSERT_SUBREG (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1873+
(ORrr (i32 G0), (i32 G0)), sub_even),
1874+
(i32 IntRegs:$a2), sub_odd)>;
1875+
18671876
// extract_vector
18681877
def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
18691878
(i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;

‎llvm/lib/Target/Sparc/SparcRegisterInfo.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,9 @@ def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
126126
def WSTATE : SparcCtrlReg<14, "WSTATE">;
127127

128128
// Integer registers
129-
def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129+
def G0 : Ri< 0, "G0">, DwarfRegNum<[0]> {
130+
let isConstant = true;
131+
}
130132
def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
131133
def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
132134
def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
@@ -378,3 +380,4 @@ let isAllocatable = 0 in {
378380
def PRRegs : RegisterClass<"SP", [i64], 64,
379381
(add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
380382
CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;
383+

‎llvm/test/CodeGen/SPARC/64bit.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,11 @@ define i64 @sra_reg(i64 %a, i64 %b) {
4040
; restore %g0, %g0, %o0
4141
;
4242
; CHECK: ret_imm0
43-
; CHECK: mov 0, %i0
43+
; CHECK: mov %g0, %i0
4444

4545
; OPT: ret_imm0
4646
; OPT: retl
47-
; OPT: mov 0, %o0
47+
; OPT: mov %g0, %o0
4848
define i64 @ret_imm0() {
4949
ret i64 0
5050
}

‎llvm/test/CodeGen/SPARC/64cond.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,9 +112,9 @@ entry:
112112
}
113113

114114
; CHECK-LABEL: setcc_resultty
115-
; CHECK-DAG: mov 0, %o0
115+
; CHECK-DAG: mov %g0, %o0
116116
; CHECK-DAG: mov %i0, %o1
117-
; CHECK-DAG: mov %o0, %o2
117+
; CHECK-DAG: mov %g0, %o2
118118
; CHECK-DAG: mov 32, %o3
119119
; CHECK-DAG: call __multi3
120120
; CHECK: movrnz %o0, 1, [[R:%[gilo][0-7]]]

‎llvm/test/CodeGen/SPARC/atomics.ll

Lines changed: 40 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -87,25 +87,24 @@ entry:
8787
; SPARC: sll %o4, %o1, %o4
8888
; SPARC: and %o0, 255, %o0
8989
; SPARC: sll %o0, %o1, %o0
90-
; SPARC: andn %g2, %o5, %g2
91-
; SPARC: mov %g0, %o5
90+
; SPARC: andn %g2, %o5, %o5
9291
; SPARC: [[LABEL1:\.L.*]]:
93-
; SPARC: or %g2, %o4, %g3
94-
; SPARC: or %g2, %o0, %g4
95-
; SPARC: cas [%o2], %g4, %g3
96-
; SPARC: cmp %g3, %g4
97-
; SPARC: mov %o5, %g4
92+
; SPARC: or %o5, %o4, %g2
93+
; SPARC: or %o5, %o0, %g3
94+
; SPARC: cas [%o2], %g3, %g2
95+
; SPARC: mov %g0, %g4
96+
; SPARC: cmp %g2, %g3
9897
; SPARC: move %icc, 1, %g4
9998
; SPARC: cmp %g4, 0
10099
; SPARC: bne %icc, [[LABEL2:\.L.*]]
101100
; SPARC: nop
102-
; SPARC: and %g3, %o3, %g4
103-
; SPARC: cmp %g2, %g4
101+
; SPARC: and %g2, %o3, %g3
102+
; SPARC: cmp %o5, %g3
104103
; SPARC: bne %icc, [[LABEL1]]
105-
; SPARC: mov %g4, %g2
104+
; SPARC: mov %g3, %o5
106105
; SPARC: [[LABEL2]]:
107106
; SPARC: retl
108-
; SPARC: srl %g3, %o1, %o0
107+
; SPARC: srl %g2, %o1, %o0
109108
; SPARC64-LABEL: test_cmpxchg_i8
110109
; SPARC64: and %o1, -4, %o2
111110
; SPARC64: mov 3, %o3
@@ -119,25 +118,24 @@ entry:
119118
; SPARC64: sll %o4, %o1, %o4
120119
; SPARC64: and %o0, 255, %o0
121120
; SPARC64: sll %o0, %o1, %o0
122-
; SPARC64: andn %g2, %o5, %g2
123-
; SPARC64: mov %g0, %o5
121+
; SPARC64: andn %g2, %o5, %o5
124122
; SPARC64: [[LABEL1:\.L.*]]:
125-
; SPARC64: or %g2, %o4, %g3
126-
; SPARC64: or %g2, %o0, %g4
127-
; SPARC64: cas [%o2], %g4, %g3
128-
; SPARC64: cmp %g3, %g4
129-
; SPARC64: mov %o5, %g4
123+
; SPARC64: or %o5, %o4, %g2
124+
; SPARC64: or %o5, %o0, %g3
125+
; SPARC64: cas [%o2], %g3, %g2
126+
; SPARC64: mov %g0, %g4
127+
; SPARC64: cmp %g2, %g3
130128
; SPARC64: move %icc, 1, %g4
131129
; SPARC64: cmp %g4, 0
132130
; SPARC64: bne %icc, [[LABEL2:\.L.*]]
133131
; SPARC64: nop
134-
; SPARC64: and %g3, %o3, %g4
135-
; SPARC64: cmp %g2, %g4
132+
; SPARC64: and %g2, %o3, %g3
133+
; SPARC64: cmp %o5, %g3
136134
; SPARC64: bne %icc, [[LABEL1]]
137-
; SPARC64: mov %g4, %g2
135+
; SPARC64: mov %g3, %o5
138136
; SPARC64: [[LABEL2]]:
139137
; SPARC64: retl
140-
; SPARC64: srl %g3, %o1, %o0
138+
; SPARC64: srl %g2, %o1, %o0
141139
define i8 @test_cmpxchg_i8(i8 %a, i8* %ptr) {
142140
entry:
143141
%pair = cmpxchg i8* %ptr, i8 %a, i8 123 monotonic monotonic
@@ -160,25 +158,24 @@ entry:
160158
; SPARC: mov 123, %o0
161159
; SPARC: sll %o0, %o1, %o0
162160
; SPARC: sll %o4, %o1, %o4
163-
; SPARC: andn %g2, %o5, %g2
164-
; SPARC: mov %g0, %o5
161+
; SPARC: andn %g2, %o5, %o5
165162
; SPARC: [[LABEL1:\.L.*]]:
166-
; SPARC: or %g2, %o0, %g3
167-
; SPARC: or %g2, %o4, %g4
168-
; SPARC: cas [%o2], %g4, %g3
169-
; SPARC: cmp %g3, %g4
170-
; SPARC: mov %o5, %g4
163+
; SPARC: or %o5, %o0, %g2
164+
; SPARC: or %o5, %o4, %g3
165+
; SPARC: cas [%o2], %g3, %g2
166+
; SPARC: mov %g0, %g4
167+
; SPARC: cmp %g2, %g3
171168
; SPARC: move %icc, 1, %g4
172169
; SPARC: cmp %g4, 0
173170
; SPARC: bne %icc, [[LABEL2:\.L.*]]
174171
; SPARC: nop
175-
; SPARC: and %g3, %o3, %g4
176-
; SPARC: cmp %g2, %g4
172+
; SPARC: and %g2, %o3, %g3
173+
; SPARC: cmp %o5, %g3
177174
; SPARC: bne %icc, [[LABEL1]]
178-
; SPARC: mov %g4, %g2
175+
; SPARC: mov %g3, %o5
179176
; SPARC: [[LABEL2]]:
180177
; SPARC: retl
181-
; SPARC: srl %g3, %o1, %o0
178+
; SPARC: srl %g2, %o1, %o0
182179
; SPARC64: and %o1, -4, %o2
183180
; SPARC64: and %o1, 3, %o1
184181
; SPARC64: xor %o1, 2, %o1
@@ -192,25 +189,24 @@ entry:
192189
; SPARC64: mov 123, %o0
193190
; SPARC64: sll %o0, %o1, %o0
194191
; SPARC64: sll %o4, %o1, %o4
195-
; SPARC64: andn %g2, %o5, %g2
196-
; SPARC64: mov %g0, %o5
192+
; SPARC64: andn %g2, %o5, %o5
197193
; SPARC64: [[LABEL1:\.L.*]]:
198-
; SPARC64: or %g2, %o0, %g3
199-
; SPARC64: or %g2, %o4, %g4
200-
; SPARC64: cas [%o2], %g4, %g3
201-
; SPARC64: cmp %g3, %g4
202-
; SPARC64: mov %o5, %g4
194+
; SPARC64: or %o5, %o0, %g2
195+
; SPARC64: or %o5, %o4, %g3
196+
; SPARC64: cas [%o2], %g3, %g2
197+
; SPARC64: mov %g0, %g4
198+
; SPARC64: cmp %g2, %g3
203199
; SPARC64: move %icc, 1, %g4
204200
; SPARC64: cmp %g4, 0
205201
; SPARC64: bne %icc, [[LABEL2:\.L.*]]
206202
; SPARC64: nop
207-
; SPARC64: and %g3, %o3, %g4
208-
; SPARC64: cmp %g2, %g4
203+
; SPARC64: and %g2, %o3, %g3
204+
; SPARC64: cmp %o5, %g3
209205
; SPARC64: bne %icc, [[LABEL1]]
210-
; SPARC64: mov %g4, %g2
206+
; SPARC64: mov %g3, %o5
211207
; SPARC64: [[LABEL2]]:
212208
; SPARC64: retl
213-
; SPARC64: srl %g3, %o1, %o0
209+
; SPARC64: srl %g2, %o1, %o0
214210
define i16 @test_cmpxchg_i16(i16 %a, i16* %ptr) {
215211
entry:
216212
%pair = cmpxchg i16* %ptr, i16 %a, i16 123 monotonic monotonic
@@ -305,14 +301,12 @@ entry:
305301

306302
; SPARC-LABEL: test_load_add_i32
307303
; SPARC: membar
308-
; SPARC: mov %g0
309304
; SPARC: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
310305
; SPARC: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
311306
; SPARC: cas [%o0], [[V]], [[V2]]
312307
; SPARC: membar
313308
; SPARC64-LABEL: test_load_add_i32
314309
; SPARC64: membar
315-
; SPARC64: mov %g0
316310
; SPARC64: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
317311
; SPARC64: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
318312
; SPARC64: cas [%o0], [[V]], [[V2]]

‎llvm/test/CodeGen/SPARC/bigreturn.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,7 @@ define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) {
137137
; SPARC-NEXT: .cfi_register %o7, %i7
138138
; SPARC-NEXT: mov %g0, %i4
139139
; SPARC-NEXT: ldd [%i2], %i0
140-
; SPARC-NEXT: mov %i4, %i5
140+
; SPARC-NEXT: mov %g0, %i5
141141
; SPARC-NEXT: std %i4, [%i2]
142142
; SPARC-NEXT: ldd [%i3], %i2
143143
; SPARC-NEXT: restore

‎llvm/test/CodeGen/SPARC/cttz.ll

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,7 @@ define i32 @f(i32 %x) {
55
; CHECK-LABEL: f:
66
; CHECK: .cfi_startproc
77
; CHECK-NEXT: ! %bb.0: ! %entry
8-
; CHECK-NEXT: mov %g0, %o1
9-
; CHECK-NEXT: sub %o1, %o0, %o1
8+
; CHECK-NEXT: sub %g0, %o0, %o1
109
; CHECK-NEXT: and %o0, %o1, %o1
1110
; CHECK-NEXT: sethi 122669, %o2
1211
; CHECK-NEXT: or %o2, 305, %o2
@@ -32,30 +31,29 @@ define i64 @g(i64 %x) {
3231
; CHECK-LABEL: g:
3332
; CHECK: .cfi_startproc
3433
; CHECK-NEXT: ! %bb.0: ! %entry
35-
; CHECK-NEXT: mov %g0, %o2
36-
; CHECK-NEXT: sub %o2, %o1, %o3
37-
; CHECK-NEXT: and %o1, %o3, %o3
38-
; CHECK-NEXT: sethi 122669, %o4
39-
; CHECK-NEXT: or %o4, 305, %o4
40-
; CHECK-NEXT: smul %o3, %o4, %o3
41-
; CHECK-NEXT: sethi %hi(.LCPI1_0), %o5
42-
; CHECK-NEXT: add %o5, %lo(.LCPI1_0), %o5
43-
; CHECK-NEXT: sub %o2, %o0, %g2
44-
; CHECK-NEXT: and %o0, %g2, %g2
45-
; CHECK-NEXT: smul %g2, %o4, %o4
46-
; CHECK-NEXT: srl %o4, 27, %o4
47-
; CHECK-NEXT: ldub [%o5+%o4], %o4
34+
; CHECK-NEXT: sub %g0, %o1, %o2
35+
; CHECK-NEXT: and %o1, %o2, %o2
36+
; CHECK-NEXT: sethi 122669, %o3
37+
; CHECK-NEXT: or %o3, 305, %o3
38+
; CHECK-NEXT: smul %o2, %o3, %o2
39+
; CHECK-NEXT: sethi %hi(.LCPI1_0), %o4
40+
; CHECK-NEXT: add %o4, %lo(.LCPI1_0), %o4
41+
; CHECK-NEXT: sub %g0, %o0, %o5
42+
; CHECK-NEXT: and %o0, %o5, %o5
43+
; CHECK-NEXT: smul %o5, %o3, %o3
4844
; CHECK-NEXT: srl %o3, 27, %o3
49-
; CHECK-NEXT: ldub [%o5+%o3], %o5
50-
; CHECK-NEXT: add %o4, 32, %o3
45+
; CHECK-NEXT: ldub [%o4+%o3], %o3
46+
; CHECK-NEXT: srl %o2, 27, %o2
47+
; CHECK-NEXT: ldub [%o4+%o2], %o4
48+
; CHECK-NEXT: add %o3, 32, %o2
5149
; CHECK-NEXT: cmp %o1, 0
52-
; CHECK-NEXT: movne %icc, %o5, %o3
50+
; CHECK-NEXT: movne %icc, %o4, %o2
5351
; CHECK-NEXT: or %o1, %o0, %o0
5452
; CHECK-NEXT: cmp %o0, 0
55-
; CHECK-NEXT: move %icc, 0, %o3
56-
; CHECK-NEXT: mov %o2, %o0
53+
; CHECK-NEXT: move %icc, 0, %o2
54+
; CHECK-NEXT: mov %g0, %o0
5755
; CHECK-NEXT: retl
58-
; CHECK-NEXT: mov %o3, %o1
56+
; CHECK-NEXT: mov %o2, %o1
5957
entry:
6058
%0 = call i64 @llvm.cttz.i64(i64 %x, i1 true)
6159
%1 = icmp eq i64 %x, 0

‎llvm/test/CodeGen/SPARC/float-constants.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,8 @@ define <2 x i32> @bitcast() {
2020
; CHECK-LABEL: test_call
2121
; CHECK: sethi 1049856, %o0
2222
; CHECK: mov %g0, %o1
23-
; CHECK-LE: mov %g0, %o0
2423
; CHECK-LE: sethi 1049856, %o1
24+
; CHECK-LE: mov %g0, %o0
2525
declare void @a(double)
2626
define void @test_call() {
2727
call void @a(double 5.0)
@@ -37,9 +37,9 @@ define void @test_call() {
3737
; CHECK: sethi 1048576, %o0
3838
; CHECK: mov %g0, %o1
3939
; CHECK: mov %o0, %o2
40-
; CHECK: mov %o1, %o3
41-
; CHECK-LE: mov %g0, %o0
40+
; CHECK: mov %g0, %o3
4241
; CHECK-LE: sethi 1048576, %o1
42+
; CHECK-LE: mov %g0, %o0
4343
declare double @llvm.pow.f64(double, double)
4444
define double @test_intrins_call() {
4545
%1 = call double @llvm.pow.f64(double 2.0, double 2.0)

‎llvm/test/CodeGen/SPARC/fshl.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ define i32 @PR47303() {
3131
; CHECK: .cfi_startproc
3232
; CHECK-NEXT: ! %bb.0: ! %bb
3333
; CHECK-NEXT: retl
34-
; CHECK-NEXT: mov 0, %o0
34+
; CHECK-NEXT: mov %g0, %o0
3535
bb:
3636
%i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
3737
%i1 = add <4 x i64> %i, zeroinitializer

‎llvm/test/CodeGen/SPARC/inlineasm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,8 +84,8 @@ attributes #0 = { "frame-pointer"="all" }
8484

8585
;; Ensures that tied in and out gets allocated properly.
8686
; CHECK-LABEL: test_i64_inout:
87-
; CHECK: mov %g0, %i2
8887
; CHECK: mov 5, %i3
88+
; CHECK: mov %g0, %i2
8989
; CHECK: xor %i2, %g0, %i2
9090
; CHECK: mov %i2, %i0
9191
; CHECK: ret

‎llvm/test/CodeGen/SPARC/missinglabel.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,7 @@ define void @f(i64 %a0) align 2 {
1313
; CHECK-NEXT: nop
1414
; CHECK-NEXT: ! %bb.1: ! %cond.false
1515
; CHECK-NEXT: .LBB0_2: ! %targetblock
16-
; CHECK-NEXT: mov %g0, %o0
17-
; CHECK-NEXT: cmp %o0, 0
16+
; CHECK-NEXT: cmp %g0, 0
1817
; CHECK-NEXT: bne %icc, .LBB0_4
1918
; CHECK-NEXT: nop
2019
; CHECK-NEXT: ! %bb.3: ! %cond.false.i83

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