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arsenmarsenm
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GlobalISel: Add G_ASSERT_ALIGN hint instruction
Insert it for call return values only for now, which is the only case the DAG handles also.
1 parent 9be193b commit 07ddfa9

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11 files changed

+363
-18
lines changed

11 files changed

+363
-18
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -836,17 +836,38 @@ class MachineIRBuilder {
836836
/// \return a MachineInstrBuilder for the newly created instruction.
837837
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
838838

839+
840+
/// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
841+
///
842+
/// \return a MachineInstrBuilder for the newly created instruction.
843+
MachineInstrBuilder buildAssertOp(unsigned Opc, const DstOp &Res, const SrcOp &Op,
844+
unsigned Val) {
845+
return buildInstr(Opc, Res, Op).addImm(Val);
846+
}
847+
839848
/// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
840849
///
841850
/// \return a MachineInstrBuilder for the newly created instruction.
842851
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
843-
unsigned Size);
852+
unsigned Size) {
853+
return buildAssertOp(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
854+
}
844855

845856
/// Build and insert \p Res = G_ASSERT_SEXT Op, Size
846857
///
847858
/// \return a MachineInstrBuilder for the newly created instruction.
848859
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
849-
unsigned Size);
860+
unsigned Size) {
861+
return buildAssertOp(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
862+
}
863+
864+
/// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
865+
///
866+
/// \return a MachineInstrBuilder for the newly created instruction.
867+
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op,
868+
Align AlignVal) {
869+
return buildAssertOp(TargetOpcode::G_ASSERT_ALIGN, Res, Op, AlignVal.value());
870+
}
850871

851872
/// Build and insert `Res = G_LOAD Addr, MMO`.
852873
///

‎llvm/include/llvm/Support/TargetOpcodes.def

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -228,10 +228,11 @@ HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
228228
/// generate code. These instructions only act as optimization hints.
229229
HANDLE_TARGET_OPCODE(G_ASSERT_SEXT)
230230
HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT)
231+
HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN)
231232
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START,
232233
G_ASSERT_SEXT)
233234
HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END,
234-
G_ASSERT_ZEXT)
235+
G_ASSERT_ALIGN)
235236

236237
/// Generic ADD instruction. This is an integer add.
237238
HANDLE_TARGET_OPCODE(G_ADD)

‎llvm/include/llvm/Target/GenericOpcodes.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1434,3 +1434,10 @@ def G_ASSERT_SEXT : GenericInstruction {
14341434
let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
14351435
let hasSideEffects = false;
14361436
}
1437+
1438+
// Asserts that a value has at least the given alignment.
1439+
def G_ASSERT_ALIGN : GenericInstruction {
1440+
let OutOperandList = (outs type0:$dst);
1441+
let InOperandList = (ins type0:$src, untyped_imm_0:$align);
1442+
let hasSideEffects = false;
1443+
}

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
8686
CallLoweringInfo Info;
8787
const DataLayout &DL = MIRBuilder.getDataLayout();
8888
MachineFunction &MF = MIRBuilder.getMF();
89+
MachineRegisterInfo &MRI = MF.getRegInfo();
8990
bool CanBeTailCalled = CB.isTailCall() &&
9091
isInTailCallPosition(CB, MF.getTarget()) &&
9192
(MF.getFunction()
@@ -109,6 +110,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
109110
CanBeTailCalled = false;
110111
}
111112

113+
112114
// First step is to marshall all the function's parameters into the correct
113115
// physregs and memory locations. Gather the sequence of argument types that
114116
// we'll pass to the assigner function.
@@ -136,18 +138,39 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
136138
else
137139
Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
138140

141+
Register ReturnHintAlignReg;
142+
Align ReturnHintAlign;
143+
139144
Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, ISD::ArgFlagsTy{}};
140-
if (!Info.OrigRet.Ty->isVoidTy())
145+
146+
if (!Info.OrigRet.Ty->isVoidTy()) {
141147
setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB);
142148

149+
if (MaybeAlign Alignment = CB.getRetAlign()) {
150+
if (*Alignment > Align(1)) {
151+
ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
152+
ReturnHintAlign = *Alignment;
153+
std::swap(Info.OrigRet.Regs[0], ReturnHintAlignReg);
154+
}
155+
}
156+
}
157+
143158
Info.CB = &CB;
144159
Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
145160
Info.CallConv = CallConv;
146161
Info.SwiftErrorVReg = SwiftErrorVReg;
147162
Info.IsMustTailCall = CB.isMustTailCall();
148163
Info.IsTailCall = CanBeTailCalled;
149164
Info.IsVarArg = IsVarArg;
150-
return lowerCall(MIRBuilder, Info);
165+
if (!lowerCall(MIRBuilder, Info))
166+
return false;
167+
168+
if (ReturnHintAlignReg) {
169+
MIRBuilder.buildAssertAlign(ReturnHintAlignReg, Info.OrigRet.Regs[0],
170+
ReturnHintAlign);
171+
}
172+
173+
return true;
151174
}
152175

153176
template <typename FuncInfoTy>

‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,11 @@ Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
3737
switch (MI->getOpcode()) {
3838
case TargetOpcode::COPY:
3939
return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
40+
case TargetOpcode::G_ASSERT_ALIGN: {
41+
// TODO: Min with source
42+
int64_t LogAlign = MI->getOperand(2).getImm();
43+
return Align(1u << LogAlign);
44+
}
4045
case TargetOpcode::G_FRAME_INDEX: {
4146
int FrameIdx = MI->getOperand(1).getIndex();
4247
return MF.getFrameInfo().getObjectAlign(FrameIdx);
@@ -466,6 +471,18 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
466471
Known.Zero.setBitsFrom(SrcBitWidth);
467472
break;
468473
}
474+
case TargetOpcode::G_ASSERT_ALIGN: {
475+
int64_t LogOfAlign = MI.getOperand(2).getImm();
476+
if (LogOfAlign == 0)
477+
break;
478+
479+
// TODO: Should use maximum with source
480+
// If a node is guaranteed to be aligned, set low zero bits accordingly as
481+
// well as clearing one bits.
482+
Known.Zero.setLowBits(LogOfAlign);
483+
Known.One.clearLowBits(LogOfAlign);
484+
break;
485+
}
469486
case TargetOpcode::G_MERGE_VALUES: {
470487
unsigned NumOps = MI.getNumOperands();
471488
unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

‎llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -282,18 +282,6 @@ MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
282282
return buildInstr(TargetOpcode::COPY, Res, Op);
283283
}
284284

285-
MachineInstrBuilder MachineIRBuilder::buildAssertSExt(const DstOp &Res,
286-
const SrcOp &Op,
287-
unsigned Size) {
288-
return buildInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op).addImm(Size);
289-
}
290-
291-
MachineInstrBuilder MachineIRBuilder::buildAssertZExt(const DstOp &Res,
292-
const SrcOp &Op,
293-
unsigned Size) {
294-
return buildInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op).addImm(Size);
295-
}
296-
297285
MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
298286
const ConstantInt &Val) {
299287
LLT Ty = Res.getLLTTy(*getMRI());

‎llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -626,7 +626,8 @@ bool RegBankSelect::assignInstr(MachineInstr &MI) {
626626
unsigned Opc = MI.getOpcode();
627627
if (isPreISelGenericOptimizationHint(Opc)) {
628628
assert((Opc == TargetOpcode::G_ASSERT_ZEXT ||
629-
Opc == TargetOpcode::G_ASSERT_SEXT) &&
629+
Opc == TargetOpcode::G_ASSERT_SEXT ||
630+
Opc == TargetOpcode::G_ASSERT_ALIGN) &&
630631
"Unexpected hint opcode!");
631632
// The only correct mapping for these is to always use the source register
632633
// bank.

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3363,6 +3363,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
33633363
case ISD::AssertAlign: {
33643364
unsigned LogOfAlign = Log2(cast<AssertAlignSDNode>(Op)->getAlign());
33653365
assert(LogOfAlign != 0);
3366+
3367+
// TODO: Should use maximum with source
33663368
// If a node is guaranteed to be aligned, set low zero bits accordingly as
33673369
// well as clearing one bits.
33683370
Known.Zero.setLowBits(LogOfAlign);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,168 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs -o - %s | FileCheck %s
3+
4+
; TODO: Could potentially insert it here
5+
define void @arg_align_8(i8 addrspace(1)* align 8 %arg0) {
6+
; CHECK-LABEL: name: arg_align_8
7+
; CHECK: bb.1 (%ir-block.0):
8+
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
9+
; CHECK-NEXT: {{ $}}
10+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
11+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
12+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
13+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
14+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
15+
; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p1) :: (store (s8) into %ir.arg0, align 8, addrspace 1)
16+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
17+
; CHECK-NEXT: S_SETPC_B64_return [[COPY3]]
18+
store i8 0, i8 addrspace(1)* %arg0, align 8
19+
ret void
20+
}
21+
22+
declare i8 addrspace(1)* @returns_ptr()
23+
declare align 8 i8 addrspace(1)* @returns_ptr_align8()
24+
25+
define void @call_result_align_1() {
26+
; CHECK-LABEL: name: call_result_align_1
27+
; CHECK: bb.1 (%ir-block.0):
28+
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
29+
; CHECK-NEXT: {{ $}}
30+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
31+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14
32+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13
33+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12
34+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
35+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
36+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
37+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
38+
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
39+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
40+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
41+
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @returns_ptr
42+
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
43+
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
44+
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
45+
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
46+
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
47+
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
48+
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
49+
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
50+
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
51+
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY17]](<4 x s32>)
52+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
53+
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
54+
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
55+
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
56+
; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)
57+
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
58+
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
59+
; CHECK-NEXT: $vgpr31 = COPY [[COPY16]](s32)
60+
; CHECK-NEXT: $sgpr30_sgpr31 = G_SI_CALL [[GV]](p0), @returns_ptr, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
61+
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr0
62+
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr1
63+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)
64+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
65+
; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p1) :: (store (s8) into %ir.ptr, addrspace 1)
66+
; CHECK-NEXT: [[COPY20:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
67+
; CHECK-NEXT: S_SETPC_B64_return [[COPY20]]
68+
%ptr = call align 1 i8 addrspace(1)* @returns_ptr()
69+
store i8 0, i8 addrspace(1)* %ptr, align 1
70+
ret void
71+
}
72+
73+
define void @call_result_align_8() {
74+
; CHECK-LABEL: name: call_result_align_8
75+
; CHECK: bb.1 (%ir-block.0):
76+
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
77+
; CHECK-NEXT: {{ $}}
78+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
79+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14
80+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13
81+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12
82+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
83+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
84+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
85+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
86+
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
87+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
88+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
89+
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @returns_ptr
90+
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
91+
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
92+
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
93+
; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
94+
; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
95+
; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
96+
; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
97+
; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
98+
; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
99+
; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY17]](<4 x s32>)
100+
; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
101+
; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
102+
; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
103+
; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
104+
; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)
105+
; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
106+
; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
107+
; CHECK-NEXT: $vgpr31 = COPY [[COPY16]](s32)
108+
; CHECK-NEXT: $sgpr30_sgpr31 = G_SI_CALL [[GV]](p0), @returns_ptr, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
109+
; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr0
110+
; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr1
111+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)
112+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
113+
; CHECK-NEXT: [[ASSERT_ALIGN:%[0-9]+]]:_(p1) = G_ASSERT_ALIGN [[MV]], 8
114+
; CHECK-NEXT: G_STORE [[C]](s8), [[ASSERT_ALIGN]](p1) :: (store (s8) into %ir.ptr, align 8, addrspace 1)
115+
; CHECK-NEXT: [[COPY20:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
116+
; CHECK-NEXT: S_SETPC_B64_return [[COPY20]]
117+
%ptr = call align 8 i8 addrspace(1)* @returns_ptr()
118+
store i8 0, i8 addrspace(1)* %ptr, align 8
119+
ret void
120+
}
121+
122+
define void @declaration_result_align_8() {
123+
; CHECK-LABEL: name: declaration_result_align_8
124+
; CHECK: bb.1 (%ir-block.0):
125+
; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
126+
; CHECK-NEXT: {{ $}}
127+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
128+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14
129+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13
130+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12
131+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
132+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
133+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
134+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
135+
; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
136+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
137+
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
138+
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @returns_ptr_align8
139+
; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY7]]
140+
; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY6]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY5]]
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY4]]
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; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]]
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; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY17]](<4 x s32>)
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; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
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; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
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; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
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; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
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; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)
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; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)
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; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)
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; CHECK-NEXT: $vgpr31 = COPY [[COPY16]](s32)
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; CHECK-NEXT: $sgpr30_sgpr31 = G_SI_CALL [[GV]](p0), @returns_ptr_align8, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
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; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY18]](s32), [[COPY19]](s32)
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; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
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; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p1) :: (store (s8) into %ir.ptr, align 8, addrspace 1)
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; CHECK-NEXT: [[COPY20:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
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; CHECK-NEXT: S_SETPC_B64_return [[COPY20]]
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%ptr = call i8 addrspace(1)* @returns_ptr_align8()
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store i8 0, i8 addrspace(1)* %ptr, align 8
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ret void
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}

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