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TacoGrandeTXTacoGrandeTX
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Improved formatting for preprocessor conditionals.
1 parent 10b90ed commit 0198481

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+44
-43
lines changed

2 files changed

+44
-43
lines changed

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -62,30 +62,30 @@ void SystemInit(void)
6262
{
6363
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
6464
Specification to see which one). */
65-
#if defined (ENABLE_SWO)
65+
#if defined (ENABLE_SWO)
6666
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
6767
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
6868
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
69-
#endif
69+
#endif
7070

7171
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
7272
Specification to see which ones). */
73-
#if defined (ENABLE_TRACE)
73+
#if defined (ENABLE_TRACE)
7474
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
7575
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
7676
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7777
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7878
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7979
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
8080
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
81-
#endif
82-
81+
#endif
82+
8383
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
8484
for your device located at https://infocenter.nordicsemi.com/ */
8585
if (errata_12()){
8686
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
8787
}
88-
88+
8989
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
9090
for your device located at https://infocenter.nordicsemi.com/ */
9191
if (errata_16()){
@@ -154,28 +154,28 @@ void SystemInit(void)
154154
if (errata_108()){
155155
*(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F;
156156
}
157-
157+
158158
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
159159
for your device located at https://infocenter.nordicsemi.com/ */
160160
if (errata_136()){
161161
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
162162
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
163163
}
164164
}
165-
165+
166166
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
167167
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
168168
* operations are not used in your code. */
169-
#if (__FPU_USED == 1)
169+
#if (__FPU_USED == 1)
170170
SCB->CPACR |= (3UL << 20) | (3UL << 22);
171171
__DSB();
172172
__ISB();
173-
#endif
173+
#endif
174174

175175
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
176176
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
177177
normal GPIOs. */
178-
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
178+
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
179179
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
180180
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
181181
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -185,12 +185,12 @@ void SystemInit(void)
185185
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
186186
NVIC_SystemReset();
187187
}
188-
#endif
188+
#endif
189189

190190
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
191191
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
192192
reserved for PinReset and not available as normal GPIO. */
193-
#if defined (CONFIG_GPIO_AS_PINRESET)
193+
#if defined (CONFIG_GPIO_AS_PINRESET)
194194
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
195195
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
196196
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@@ -203,7 +203,7 @@ void SystemInit(void)
203203
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
204204
NVIC_SystemReset();
205205
}
206-
#endif
206+
#endif
207207

208208
SystemCoreClockUpdate();
209209

@@ -222,7 +222,7 @@ void SystemInit(void)
222222
*
223223
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
224224
*/
225-
#if defined (DEVICE_ITM)
225+
#if defined (DEVICE_ITM)
226226
/* Enable SWO trace functionality */
227227
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
228228
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
@@ -238,7 +238,7 @@ void SystemInit(void)
238238

239239
/* set prescaler */
240240
TPI->ACPR = 0;
241-
#endif
241+
#endif
242242
}
243243

244244

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c

Lines changed: 28 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
2222

2323
/* NOTE: Template files (including this one) are application specific and therefore expected to
2424
be copied into the application project folder prior to its use! */
25-
25+
2626
#include <stdint.h>
2727
#include <stdbool.h>
2828
#include "nrf.h"
@@ -59,23 +59,23 @@ void SystemInit(void)
5959
{
6060
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
6161
Specification to see which one). */
62-
#if defined (ENABLE_SWO)
62+
#if defined (ENABLE_SWO)
6363
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
6464
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
6565
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
66-
#endif
66+
#endif
6767

6868
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
6969
Specification to see which ones). */
70-
#if defined (ENABLE_TRACE)
70+
#if defined (ENABLE_TRACE)
7171
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
7272
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
7373
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7474
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7575
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7676
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7777
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
78-
#endif
78+
#endif
7979

8080
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
8181
for your device located at https://infocenter.nordicsemi.com/ */
@@ -84,7 +84,7 @@ void SystemInit(void)
8484
NRF_CLOCK->EVENTS_CTTO = 0;
8585
NRF_CLOCK->CTIV = 0;
8686
}
87-
87+
8888
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
8989
for your device located at https://infocenter.nordicsemi.com/ */
9090
if (errata_66()){
@@ -106,52 +106,52 @@ void SystemInit(void)
106106
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
107107
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
108108
}
109-
109+
110110
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
111111
for your device located at https://infocenter.nordicsemi.com/ */
112112
if (errata_98()){
113113
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
114114
}
115-
115+
116116
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
117117
for your device located at https://infocenter.nordicsemi.com/ */
118118
if (errata_103()){
119119
NRF_CCM->MAXPACKETSIZE = 0xFBul;
120120
}
121-
121+
122122
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
123123
for your device located at https://infocenter.nordicsemi.com/ */
124124
if (errata_115()){
125125
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
126126
}
127-
127+
128128
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
129129
for your device located at https://infocenter.nordicsemi.com/ */
130130
if (errata_120()){
131131
*(volatile uint32_t *)0x40029640ul = 0x200ul;
132132
}
133-
133+
134134
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
135135
for your device located at https://infocenter.nordicsemi.com/ */
136136
if (errata_136()){
137137
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
138138
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
139139
}
140140
}
141-
141+
142142
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
143143
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
144144
* operations are not used in your code. */
145-
#if (__FPU_USED == 1)
145+
#if (__FPU_USED == 1)
146146
SCB->CPACR |= (3UL << 20) | (3UL << 22);
147147
__DSB();
148148
__ISB();
149-
#endif
149+
#endif
150150

151151
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
152152
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
153153
normal GPIOs. */
154-
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
154+
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
155155
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
156156
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
157157
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -161,12 +161,12 @@ void SystemInit(void)
161161
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
162162
NVIC_SystemReset();
163163
}
164-
#endif
164+
#endif
165165

166166
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
167167
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
168168
reserved for PinReset and not available as normal GPIO. */
169-
#if defined (CONFIG_GPIO_AS_PINRESET)
169+
#if defined (CONFIG_GPIO_AS_PINRESET)
170170
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
171171
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
172172
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@@ -179,7 +179,7 @@ void SystemInit(void)
179179
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
180180
NVIC_SystemReset();
181181
}
182-
#endif
182+
#endif
183183

184184
SystemCoreClockUpdate();
185185

@@ -198,7 +198,7 @@ void SystemInit(void)
198198
*
199199
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
200200
*/
201-
#if defined (DEVICE_ITM)
201+
#if defined (DEVICE_ITM)
202202
/* Enable SWO trace functionality */
203203
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
204204
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
@@ -214,7 +214,8 @@ void SystemInit(void)
214214

215215
/* set prescaler */
216216
TPI->ACPR = 0;
217-
#endif
217+
#endif
218+
218219
}
219220

220221

@@ -223,7 +224,7 @@ static bool errata_36(void)
223224
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
224225
return true;
225226
}
226-
227+
227228
return false;
228229
}
229230

@@ -233,7 +234,7 @@ static bool errata_66(void)
233234
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
234235
return true;
235236
}
236-
237+
237238
return false;
238239
}
239240

@@ -243,7 +244,7 @@ static bool errata_98(void)
243244
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
244245
return true;
245246
}
246-
247+
247248
return false;
248249
}
249250

@@ -253,7 +254,7 @@ static bool errata_103(void)
253254
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
254255
return true;
255256
}
256-
257+
257258
return false;
258259
}
259260

@@ -263,7 +264,7 @@ static bool errata_115(void)
263264
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
264265
return true;
265266
}
266-
267+
267268
return false;
268269
}
269270

@@ -273,7 +274,7 @@ static bool errata_120(void)
273274
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
274275
return true;
275276
}
276-
277+
277278
return false;
278279
}
279280

@@ -283,7 +284,7 @@ static bool errata_136(void)
283284
if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
284285
return true;
285286
}
286-
287+
287288
return false;
288289
}
289290

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