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Cruz Monrreal
authored
Merge pull request #9102 from OpenNuvoton/nuvoton_support_boot_stack_option
Nuvoton: Support boot stack size configuration option
2 parents 8bd9772 + 28b820f commit 187d2d0

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25 files changed

+195
-101
lines changed

25 files changed

+195
-101
lines changed

‎targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@
4141
#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S)
4242
#endif
4343

44+
#if !defined(MBED_BOOT_STACK_SIZE)
45+
#define MBED_BOOT_STACK_SIZE 0x400
46+
#endif
47+
4448
#else
4549

4650
#ifndef MBED_APP_START
@@ -59,6 +63,10 @@
5963
#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S
6064
#endif
6165

66+
#if !defined(MBED_BOOT_STACK_SIZE)
67+
#define MBED_BOOT_STACK_SIZE 0x400
68+
#endif
69+
6270
#endif
6371

6472
/* Requirements for NSC location
@@ -70,15 +78,6 @@
7078
*/
7179
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
7280

73-
/* Initial/ISR stack size */
74-
#if (! defined(NU_INITIAL_STACK_SIZE))
75-
#if defined(DOMAIN_NS) && DOMAIN_NS
76-
#define NU_INITIAL_STACK_SIZE 0x800
77-
#else
78-
#define NU_INITIAL_STACK_SIZE 0x800
79-
#endif
80-
#endif
81-
8281
#if defined(DOMAIN_NS) && DOMAIN_NS
8382

8483
LR_IROM1 MBED_APP_START
@@ -91,7 +90,7 @@ LR_IROM1 MBED_APP_START
9190
.ANY (+RO)
9291
}
9392

94-
ARM_LIB_STACK MBED_RAM_APP_START EMPTY NU_INITIAL_STACK_SIZE
93+
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
9594
{
9695
}
9796

@@ -129,7 +128,7 @@ LR_IROM1 MBED_APP_START
129128
.ANY (+RO)
130129
}
131130

132-
ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE
131+
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
133132
{
134133
}
135134

‎targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@
4141
#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S)
4242
#endif
4343

44+
#if !defined(MBED_BOOT_STACK_SIZE)
45+
#define MBED_BOOT_STACK_SIZE 0x400
46+
#endif
47+
4448
#else
4549

4650
#ifndef MBED_APP_START
@@ -59,6 +63,10 @@
5963
#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S
6064
#endif
6165

66+
#if !defined(MBED_BOOT_STACK_SIZE)
67+
#define MBED_BOOT_STACK_SIZE 0x400
68+
#endif
69+
6270
#endif
6371

6472
/* Requirements for NSC location
@@ -70,15 +78,6 @@
7078
*/
7179
#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
7280

73-
/* Initial/ISR stack size */
74-
#if (! defined(NU_INITIAL_STACK_SIZE))
75-
#if defined(DOMAIN_NS) && DOMAIN_NS
76-
#define NU_INITIAL_STACK_SIZE 0x800
77-
#else
78-
#define NU_INITIAL_STACK_SIZE 0x800
79-
#endif
80-
#endif
81-
8281
#if defined(DOMAIN_NS) && DOMAIN_NS
8382

8483
LR_IROM1 MBED_APP_START
@@ -91,7 +90,7 @@ LR_IROM1 MBED_APP_START
9190
.ANY (+RO)
9291
}
9392

94-
ARM_LIB_STACK MBED_RAM_APP_START EMPTY NU_INITIAL_STACK_SIZE
93+
ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
9594
{
9695
}
9796

@@ -129,7 +128,7 @@ LR_IROM1 MBED_APP_START
129128
.ANY (+RO)
130129
}
131130

132-
ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE
131+
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
133132
{
134133
}
135134

‎targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -28,47 +28,51 @@
2828
#if defined(DOMAIN_NS) && DOMAIN_NS
2929

3030
#ifndef MBED_APP_START
31-
#define MBED_APP_START (0x10000000 + MBED_ROM_START + MBED_ROM_SIZE_S)
31+
#define MBED_APP_START (0x10000000 + MBED_ROM_START + MBED_ROM_SIZE_S)
3232
#endif
3333

3434
#ifndef MBED_APP_SIZE
35-
#define MBED_APP_SIZE (MBED_ROM_SIZE - MBED_ROM_SIZE_S)
35+
#define MBED_APP_SIZE (MBED_ROM_SIZE - MBED_ROM_SIZE_S)
3636
#endif
3737

3838
#ifndef MBED_RAM_APP_START
39-
#define MBED_RAM_APP_START (0x10000000 + MBED_RAM_START + MBED_RAM_SIZE_S)
39+
#define MBED_RAM_APP_START (0x10000000 + MBED_RAM_START + MBED_RAM_SIZE_S)
4040
#endif
4141

4242
#ifndef MBED_RAM_APP_SIZE
43-
#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S)
43+
#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S)
44+
#endif
45+
46+
#if !defined(MBED_BOOT_STACK_SIZE)
47+
#define MBED_BOOT_STACK_SIZE 0x400
4448
#endif
4549

4650
#else
4751

4852
#ifndef MBED_APP_START
49-
#define MBED_APP_START MBED_ROM_START
53+
#define MBED_APP_START MBED_ROM_START
5054
#endif
5155

5256
#ifndef MBED_APP_SIZE
53-
#define MBED_APP_SIZE MBED_ROM_SIZE_S
57+
#define MBED_APP_SIZE MBED_ROM_SIZE_S
5458
#endif
5559

5660
#ifndef MBED_RAM_APP_START
57-
#define MBED_RAM_APP_START MBED_RAM_START
61+
#define MBED_RAM_APP_START MBED_RAM_START
5862
#endif
5963

6064
#ifndef MBED_RAM_APP_SIZE
61-
#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S
65+
#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S
6266
#endif
6367

68+
#ifndef MBED_BOOT_STACK_SIZE
69+
#define MBED_BOOT_STACK_SIZE 0x400
6470
#endif
6571

66-
#if defined(DOMAIN_NS) && DOMAIN_NS
67-
StackSize = 0x800;
68-
#else
69-
StackSize = 0x800;
7072
#endif
7173

74+
StackSize = MBED_BOOT_STACK_SIZE;
75+
7276
/* Requirements for NSC location
7377
*
7478
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.

‎targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,10 @@ if (isdefinedsymbol(DOMAIN_NS)) {
3333
define symbol MBED_RAM_APP_SIZE = (MBED_RAM_SIZE - MBED_RAM_SIZE_S);
3434
}
3535

36+
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
37+
define symbol MBED_BOOT_STACK_SIZE = 0x400;
38+
}
39+
3640
/*-Specials-*/
3741
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
3842
/*-Memory Regions-*/
@@ -42,7 +46,7 @@ if (isdefinedsymbol(DOMAIN_NS)) {
4246
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
4347

4448
/*-Sizes-*/
45-
define symbol __ICFEDIT_size_cstack__ = 0x800;
49+
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
4650
define symbol __ICFEDIT_size_heap__ = 0x8000;
4751

4852
} else {
@@ -63,6 +67,10 @@ if (isdefinedsymbol(DOMAIN_NS)) {
6367
define symbol MBED_RAM_APP_SIZE = MBED_RAM_SIZE_S;
6468
}
6569

70+
if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
71+
define symbol MBED_BOOT_STACK_SIZE = 0x400;
72+
}
73+
6674
/* Requirements for NSC location
6775
*
6876
* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
@@ -87,7 +95,7 @@ if (isdefinedsymbol(DOMAIN_NS)) {
8795
define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
8896

8997
/*-Sizes-*/
90-
define symbol __ICFEDIT_size_cstack__ = 0x800;
98+
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
9199
define symbol __ICFEDIT_size_heap__ = 0x4000;
92100
}
93101

‎targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@
88
#define MBED_APP_SIZE 0x00040000
99
#endif
1010

11+
#if !defined(MBED_BOOT_STACK_SIZE)
12+
#define MBED_BOOT_STACK_SIZE 0x400
13+
#endif
14+
1115
LR_IROM1 MBED_APP_START {
1216
ER_IROM1 MBED_APP_START { ; load address = execution address
1317
*(RESET, +First)
@@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START {
1620
}
1721

1822

19-
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
23+
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
2024
}
2125

22-
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors
26+
/* VTOR[TBLOFF] alignment requires:
27+
*
28+
* 1. Minumum 32-word
29+
* 2. Rounding up to the next power of two of table size
30+
*/
31+
ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 64)) { ; Reserve for vectors
2332
}
2433

2534
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned

‎targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@
88
#define MBED_APP_SIZE 0x00040000
99
#endif
1010

11+
#if !defined(MBED_BOOT_STACK_SIZE)
12+
#define MBED_BOOT_STACK_SIZE 0x400
13+
#endif
14+
1115
LR_IROM1 MBED_APP_START {
1216
ER_IROM1 MBED_APP_START { ; load address = execution address
1317
*(RESET, +First)
@@ -16,10 +20,15 @@ LR_IROM1 MBED_APP_START {
1620
}
1721

1822

19-
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
23+
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
2024
}
21-
22-
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors
25+
26+
/* VTOR[TBLOFF] alignment requires:
27+
*
28+
* 1. Minumum 32-word
29+
* 2. Rounding up to the next power of two of table size
30+
*/
31+
ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 64)) { ; Reserve for vectors
2332
}
2433

2534
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned

‎targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,11 @@
1010
#define MBED_APP_SIZE 0x00040000
1111
#endif
1212

13-
StackSize = 0x800;
13+
#if !defined(MBED_BOOT_STACK_SIZE)
14+
#define MBED_BOOT_STACK_SIZE 0x400
15+
#endif
16+
17+
StackSize = MBED_BOOT_STACK_SIZE;
1418

1519
MEMORY
1620
{

‎targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
44
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
55
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x00040000; }
6+
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; }
67
/*-Specials-*/
78
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
89
/*-Memory Regions-*/
@@ -11,7 +12,7 @@ define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
1112
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
1213
define symbol __ICFEDIT_region_IRAM_end__ = 0x20008000 - 1;
1314
/*-Sizes-*/
14-
define symbol __ICFEDIT_size_cstack__ = 0x800;
15+
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
1516
define symbol __ICFEDIT_size_heap__ = 0x4000;
1617
/**** End of ICF editor section. ###ICF###*/
1718

‎targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8,33 +8,34 @@
88
#define MBED_APP_SIZE 0x00080000
99
#endif
1010

11+
#if !defined(MBED_BOOT_STACK_SIZE)
12+
#define MBED_BOOT_STACK_SIZE 0x400
13+
#endif
14+
15+
1116
#define SPIM_CCM_START 0x20020000
1217
#define SPIM_CCM_END 0x20028000
1318

14-
#define MBED_RAM_START 0x20000000
15-
#define MBED_RAM_SIZE 0x20000
16-
#define MBED_STACK_RAM_START (MBED_RAM_START)
17-
#define MBED_STACK_RAM_SIZE 0x800
18-
#define MBED_VECTTABLE_RAM_START (MBED_STACK_RAM_START + MBED_STACK_RAM_SIZE)
19-
#define MBED_VECTTABLE_RAM_SIZE (4*(16 + 96))
20-
#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE)
21-
#define MBED_CRASH_REPORT_RAM_SIZE 0x100
2219

2320
LR_IROM1 MBED_APP_START {
2421
ER_IROM1 MBED_APP_START { ; load address = execution address
2522
*(RESET, +First)
2623
*(InRoot$$Sections)
2724
.ANY (+RO)
2825
}
29-
30-
31-
ARM_LIB_STACK MBED_STACK_RAM_START EMPTY MBED_STACK_RAM_SIZE {
26+
27+
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
3228
}
33-
34-
ER_IRAMVEC MBED_VECTTABLE_RAM_START EMPTY MBED_VECTTABLE_RAM_SIZE { ; Reserve for vectors
29+
30+
/* VTOR[TBLOFF] alignment requires:
31+
*
32+
* 1. Minumum 32-word
33+
* 2. Rounding up to the next power of two of table size
34+
*/
35+
ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 96)) { ; Reserve for vectors
3536
}
3637

37-
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; Reserve for crash data storage
38+
RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage
3839
}
3940

4041
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned

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