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Merge pull request #6245 from mbedNoobNinja/Sync_PR
Update for VK_RZ_A1H
2 parents f3e2a3d + cf8fd20 commit 2c7f909

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‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h

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/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef RESERVED_PINS_H
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#define RESERVED_PINS_H
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‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h

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#endif
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/* <-Take measures about optimization problems of web compiler */
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#define TRANSACTION_QUEUE_SIZE_SPI 16
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#define DEVICE_ID_LENGTH 32
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#define DEVICE_MAC_OFFSET 20
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#include "objects.h"
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#include "dma_api.h"
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#endif

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c

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#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
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#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM))
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#define CS2_SDRAM
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#endif
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/******************************************************************************
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Imported global variables and functions (from other files)

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct

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#! armcc -E -I"../"
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;**************************************************
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; Copyright (c) 2017 ARM Ltd. All rights reserved.
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;**************************************************
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; Scatter-file for RTX Example on Versatile Express
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LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
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; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
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#include "mbed_config.h"
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#include "mem_VK_RZ_A1H.h"
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LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
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{
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TTB +0 EMPTY 0x4000
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{ } ; Level-1 Translation Table for MMU
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}
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SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
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SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
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{
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}
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VECTORS __VECTOR_BASE FIXED
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{
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* (RESET, +FIRST) ; Vector table and other startup code
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* (InRoot$$Sections) ; All (library) code that must be in a root region
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* (+RO-CODE) ; Application RO code (.text)
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}
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SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024)
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{
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; S-Flash ROM : Executable cached region
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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RO_DATA +0
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{ * (+RO-DATA) } ; Application RO data (.constdata)
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RW_DATA __DATA_BASE
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{ * (+RW) } ; Application RW data (.data)
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VECTORS 0x18020000 FIXED
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{
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* (RESET, +FIRST) ; Vector table and other (assembler) startup code
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* (InRoot$$Sections) ; All (library) code that must be in a root region
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* (+RO-CODE) ; Application RO code (.text)
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}
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RW_IRAM1 +0 ALIGN 0x10
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{ * (+ZI) } ; Application ZI data (.bss)
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RO_DATA +0
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{ * (+RO-DATA) } ; Application RO data (.constdata)
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ARM_LIB_HEAP +0
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{ * (HEAP) } ; Application heap area (HEAP)
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RW_DATA 0x20020000
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{ * (+RW) } ; Application RW data (.data)
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ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
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{ }
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ZI_DATA +0 ALIGN 0x400
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{ * (+ZI) } ; Application ZI data (.bss)
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; RAM-NC : Internal non-cached RAM region
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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RW_DATA_NC 0x60900000 0x00100000
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RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
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{ * (NC_DATA) } ; Application RW data Non cached area
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ZI_DATA_NC +0
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{ * (NC_BSS) } ; Application ZI data Non cached area
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}
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#ifndef RUN_FROM_SDRAM
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SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
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{
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}
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#else
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SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!)
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{
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}
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#endif

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h

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/**************************************************************************//**
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* @file mem_VK_RZ_A1H.h
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* @brief Memory base and size definitions (used in scatter file)
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* @version V1.00
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* @date 10 Mar 2017
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MEM_VK_RZ_A1H_H
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#define __MEM_VK_RZ_A1H_H
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/*----------------------------------------------------------------------------
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User Stack & Heap size definition
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*----------------------------------------------------------------------------*/
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- ROM Configuration ------------------------------------
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//
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// <h> ROM Configuration
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// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
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// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*----------------------------------------------------------------------------*/
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#ifdef RUN_FROM_SDRAM
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#define __ROM_BASE 0x08000000
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#define __ROM_SIZE 0x02000000
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#define __VECTOR_BASE 0x08000000
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#define __DATA_BASE +0 ALIGN 0x100000
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#elif defined (RUN_FROM_SRAM)
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#define __ROM_BASE 0x200A0000
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#define __ROM_SIZE 0x00960000
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#define __VECTOR_BASE 0x200A0000
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#define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS
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#else
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#define __ROM_BASE 0x18020000
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#define __ROM_SIZE 0x01FE0000
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#define __VECTOR_BASE 0x18020000
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#define __DATA_BASE 0x20020000
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#endif
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/*--------------------- RAM Configuration -----------------------------------
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*----------------------------------------------------------------------------*/
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#ifdef RUN_FROM_SDRAM
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#define __RAM_BASE 0x08000000
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#define __RAM_SIZE 0x02000000
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#define __NC_RAM_SIZE 0x00200000
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#else
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#define __RAM_BASE 0x20000000
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#define __RAM_SIZE 0x00A00000
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#define __NC_RAM_SIZE 0x00100000
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#endif
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#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
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#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
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#define __UND_STACK_SIZE 0x00000100
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#define __SVC_STACK_SIZE 0x00008000
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#define __ABT_STACK_SIZE 0x00000100
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#define __FIQ_STACK_SIZE 0x00000100
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#define __IRQ_STACK_SIZE 0x0000F000
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#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
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/*----------------------------------------------------------------------------*/
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/*--------------------- TTB Configuration ------------------------------------
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//
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// <h> TTB Configuration
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// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
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// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*----------------------------------------------------------------------------*/
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#define __TTB_BASE 0x20000000
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#define __TTB_SIZE 0x00004000
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#endif /* __MEM_VK_RZ_A1H_H */

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