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Cruz Monrreal
authored
Merge pull request #10366 from kjbracey-arm/feature_CMSIS_5_ca812421
Update CMSIS to 5.5.1
2 parents 3bda0ef + 020f0e5 commit 582edf5

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‎cmsis/TARGET_CORTEX_A/cmsis_armclang.h

Lines changed: 24 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file cmsis_armclang.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.0.2
5-
* @date 10. January 2018
4+
* @version V1.1.0
5+
* @date 18. March 2019
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
8+
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -214,7 +214,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
214214
\param [in] value Value to count the leading zeros
215215
\return number of leading zeros in value
216216
*/
217-
#define __CLZ (uint8_t)__builtin_clz
217+
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
218+
{
219+
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
220+
__builtin_clz(0) is undefined behaviour, so handle this case specially.
221+
This guarantees ARM-compatible results if happening to compile on a non-ARM
222+
target, and ensures the compiler doesn't decide to activate any
223+
optimisations using the logic "value was passed to __builtin_clz, so it
224+
is non-zero".
225+
ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
226+
single CLZ instruction.
227+
*/
228+
if (value == 0U)
229+
{
230+
return 32U;
231+
}
232+
return __builtin_clz(value);
233+
}
218234

219235
/**
220236
\brief LDR Exclusive (8 bit)
@@ -375,8 +391,8 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr()
375391
"MRS %0, cpsr \n"
376392
"CPS #0x1F \n" // no effect in USR mode
377393
"MOV %1, sp \n"
378-
"MSR cpsr_c, %2 \n" // no effect in USR mode
379-
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
394+
"MSR cpsr_c, %0 \n" // no effect in USR mode
395+
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
380396
);
381397
return result;
382398
}
@@ -391,8 +407,8 @@ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
391407
"MRS %0, cpsr \n"
392408
"CPS #0x1F \n" // no effect in USR mode
393409
"MOV sp, %1 \n"
394-
"MSR cpsr_c, %2 \n" // no effect in USR mode
395-
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
410+
"MSR cpsr_c, %0 \n" // no effect in USR mode
411+
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
396412
);
397413
}
398414

‎cmsis/TARGET_CORTEX_A/cmsis_gcc.h

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_gcc.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.0.2
5-
* @date 09. April 2018
4+
* @version V1.1.0
5+
* @date 20. December 2018
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -171,7 +171,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
171171
#else
172172
uint32_t result;
173173

174-
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
174+
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
175175
return result;
176176
#endif
177177
}
@@ -204,7 +204,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
204204
#else
205205
int16_t result;
206206

207-
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
207+
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
208208
return result;
209209
#endif
210210
}
@@ -267,7 +267,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
267267
\param [in] value Value to count the leading zeros
268268
\return number of leading zeros in value
269269
*/
270-
#define __CLZ (uint8_t)__builtin_clz
270+
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
271+
{
272+
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
273+
__builtin_clz(0) is undefined behaviour, so handle this case specially.
274+
This guarantees ARM-compatible results if happening to compile on a non-ARM
275+
target, and ensures the compiler doesn't decide to activate any
276+
optimisations using the logic "value was passed to __builtin_clz, so it
277+
is non-zero".
278+
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
279+
single CLZ instruction.
280+
*/
281+
if (value == 0U)
282+
{
283+
return 32U;
284+
}
285+
return __builtin_clz(value);
286+
}
271287

272288
/**
273289
\brief LDR Exclusive (8 bit)

‎cmsis/TARGET_CORTEX_A/cmsis_iccarm.h

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_iccarm.h
33
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4-
* @version V5.0.6
5-
* @date 02. March 2018
4+
* @version V5.0.7
5+
* @date 04. Semptember 2018
66
******************************************************************************/
77

88
//------------------------------------------------------------------------------
@@ -109,7 +109,12 @@
109109
#endif
110110

111111
#ifndef __RESTRICT
112-
#define __RESTRICT restrict
112+
#if __ICCARM_V8
113+
#define __RESTRICT __restrict
114+
#else
115+
/* Needs IAR language extensions */
116+
#define __RESTRICT restrict
117+
#endif
113118
#endif
114119

115120
#ifndef __STATIC_INLINE

‎cmsis/TARGET_CORTEX_A/core_ca.h

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
/**************************************************************************//**
22
* @file core_ca.h
33
* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
4-
* @version V1.0.1
5-
* @date 07. May 2018
4+
* @version V1.0.2
5+
* @date 12. November 2018
66
******************************************************************************/
77
/*
8-
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
8+
* Copyright (c) 2009-2018 ARM Limited. All rights reserved.
99
*
1010
* SPDX-License-Identifier: Apache-2.0
1111
*
@@ -28,13 +28,12 @@
2828
#pragma clang system_header /* treat file as system include file */
2929
#endif
3030

31-
#ifdef __cplusplus
32-
extern "C" {
33-
#endif
34-
3531
#ifndef __CORE_CA_H_GENERIC
3632
#define __CORE_CA_H_GENERIC
3733

34+
#ifdef __cplusplus
35+
extern "C" {
36+
#endif
3837

3938
/*******************************************************************************
4039
* CMSIS definitions

‎cmsis/TARGET_CORTEX_M/cmsis_armcc.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_armcc.h
33
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4-
* @version V5.0.4
5-
* @date 10. January 2018
4+
* @version V5.0.5
5+
* @date 14. December 2018
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -47,6 +47,10 @@
4747
/* __ARM_ARCH_8M_BASE__ not applicable */
4848
/* __ARM_ARCH_8M_MAIN__ not applicable */
4949

50+
/* CMSIS compiler control DSP macros */
51+
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
52+
#define __ARM_FEATURE_DSP 1
53+
#endif
5054

5155
/* CMSIS compiler specific defines */
5256
#ifndef __ASM

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