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Cruz Monrreal
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Merge pull request #9089 from jeromecoutant/DEV_QSPI_TEST
STM32 QSPI update
2 parents 6380d88 + 9790f67 commit 64e7e46

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‎TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_MX25L51245G_H
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#define MBED_QSPI_FLASH_MX25L51245G_H
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#define QSPI_FLASH_CHIP_STRING "macronix MX25L51245G"
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// Command for reading status register
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#define QSPI_CMD_RDSR 0x05
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// Command for reading configuration register
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#define QSPI_CMD_RDCR0 0x15
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// Command for writing status/configuration register
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#define QSPI_CMD_WRSR 0x01
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// Command for reading security register
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#define QSPI_CMD_RDSCUR 0x2B
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// Command for setting Reset Enable
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#define QSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define QSPI_CMD_RST 0x99
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// Command for setting write enable
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#define QSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define QSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define QSPI_WRSR_MAX_TIME 34500 // 30ms
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// general wait max time [us]
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#define QSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
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#define QSPI_PAGE_SIZE 256 // 256B
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#define QSPI_SECTOR_SIZE 4096 // 4kB
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#define QSPI_SECTOR_COUNT 2048 //
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// Commands for reading
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#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
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#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
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#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
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#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
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#define QSPI_READ_1IO_DUMMY_CYCLE 0
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#define QSPI_READ_FAST_DUMMY_CYCLE 8
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#define QSPI_READ_2IO_DUMMY_CYCLE 4
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#define QSPI_READ_1I2O_DUMMY_CYCLE 8
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#define QSPI_READ_4IO_DUMMY_CYCLE 6
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#define QSPI_READ_1I4O_DUMMY_CYCLE 8
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
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#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
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#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 1200000 // 1s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
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// max frequency for basic rw operation (for fast mode)
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#define QSPI_COMMON_MAX_FREQUENCY 32000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 2
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#define QSPI_SECURITY_REG_SIZE 1
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#define QSPI_MAX_REG_SIZE 2
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) //
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#define STATUS_BIT_BP1 (1 << 3) //
97+
#define STATUS_BIT_BP2 (1 << 4) //
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#define STATUS_BIT_BP3 (1 << 5) //
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#define STATUS_BIT_QE (1 << 6) // Quad Enable
100+
#define STATUS_BIT_SRWD (1 << 7) // status register write protect
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// configuration register 0
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// bit 0, 1, 2, 4, 5, 7 reserved
104+
#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
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#endif // MBED_QSPI_FLASH_MX25L51245G_H

‎TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_F413ZH/flash_config.h

Lines changed: 0 additions & 22 deletions
This file was deleted.

‎TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h

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This file was deleted.

‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

Lines changed: 30 additions & 4 deletions
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@@ -18,19 +18,45 @@
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#define MBED_FLASH_CONFIGS_H
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2020
#if defined(TARGET_DISCO_L475VG_IOT01A)
21-
#include "STM/DISCO_L475VG_IOT01A/flash_config.h"
21+
#include "MX25RXX35F_config.h" // MX25R6435F
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#elif defined(TARGET_DISCO_F413ZH)
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#include "N25Q128A_config.h" // N25Q128A13EF840F
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#elif defined(TARGET_DISCO_F746NG)
27+
#include "N25Q128A_config.h" // N25Q128A13EF840E
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#elif defined(TARGET_DISCO_F469NI)
30+
#include "N25Q128A_config.h" // N25Q128A13EF840E
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#elif defined(TARGET_DISCO_F769NI)
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#include "MX25L51245G_config.h" // MX25L51245G
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#elif defined(TARGET_DISCO_L476VG)
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#include "N25Q128A_config.h" // N25Q128A13EF840E
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/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
38+
#undef QSPI_CMD_READ_DPI
39+
#undef QSPI_CMD_READ_QPI
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#undef QSPI_CMD_WRITE_DPI
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#undef QSPI_CMD_WRITE_QPI
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#elif defined(TARGET_DISCO_L496AG)
44+
#include "MX25RXX35F_config.h" // MX25R6435F
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2246
#elif defined(TARGET_NRF52840)
2347
#include "NORDIC/NRF52840_DK/flash_config.h"
24-
#elif defined(TARGET_DISCO_F413ZH)
25-
#include "STM/DISCO_F413ZH/flash_config.h"
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2649
#elif defined(TARGET_EFM32GG11_STK3701)
2750
#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"
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2852
#elif defined(TARGET_K82F)
2953
#include "NXP/K82F/flash_config.h"
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3055
#elif defined(TARGET_KL82Z)
3156
#include "NXP/KL82Z/flash_config.h"
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3258
#elif defined(TARGET_LPC546XX)
3359
#include "NXP/LPC546XX/flash_config.h"
34-
#endif
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61+
#endif
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#endif // MBED_FLASH_CONFIGS_H

‎components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json

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@@ -20,9 +20,18 @@
2020
"DISCO_L476VG": {
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"QSPI_FREQ": "80000000"
2222
},
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"DISCO_L496AG": {
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"QSPI_FREQ": "8000000"
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},
2326
"DISCO_F469NI": {
2427
"QSPI_FREQ": "80000000"
2528
},
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"DISCO_F746NG": {
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"QSPI_FREQ": "80000000"
31+
},
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"DISCO_F769NI": {
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"QSPI_FREQ": "8000000"
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},
2635
"NRF52840_DK": {
2736
"QSPI_FREQ": "32000000"
2837
}

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PeripheralPins.c

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Original file line numberDiff line numberDiff line change
@@ -352,30 +352,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
352352

353353
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
354354
{PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
355-
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
356-
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
357355
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
358-
{PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
359-
{PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
360356
{PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
361357
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
362358
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
363-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
364359
{PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
365360
{PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
366361
{PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
367362
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
368-
{PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
369-
{PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
370-
{PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
371-
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
372363
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
373364
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
374365
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
375366
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
376367
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
377-
{PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
378-
{PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
379368
{NC, NC, 0}
380369
};
381370

@@ -388,7 +377,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
388377

389378
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
390379
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
391-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
392380
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
393381
{NC, NC, 0}
394382
};

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/PinNames.h

Lines changed: 0 additions & 8 deletions
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@@ -307,14 +307,6 @@ typedef enum {
307307
SYS_WKUP2 = PC_0,
308308
SYS_WKUP3 = PC_1,
309309

310-
/**** QSPI pins ****/
311-
QSPI1_IO0 = PD_11,
312-
QSPI1_IO1 = PD_12,
313-
QSPI1_IO2 = PE_2,
314-
QSPI1_IO3 = PD_13,
315-
QSPI1_SCK = PB_2,
316-
QSPI1_CSN = PB_6,
317-
318310
// Not connected
319311
NC = (int)0xFFFFFFFF
320312
} PinName;

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/PeripheralPins.c

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -404,30 +404,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
404404

405405
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
406406
{PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_A1
407-
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to SD_CMD
408-
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to DFSDM2_DATIN1
409407
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4
410-
{PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to ARD_A5
411-
{PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LED2_GREEN
412408
{PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to SD_D0
413409
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to SD_D1
414410
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to SD_D2
415-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3
416411
{PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 // Connected to PSRAM_A16 [IS66WV51216EBLL_A16]
417412
{PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 // Connected to PSRAM_A17 [IS66WV51216EBLL_A17]
418413
{PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 [N25Q128A13EF840F_DQ3]
419414
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 [N25Q128A13EF840F_DQ2]
420-
{PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0 // Connected to LCD_PSRAM_D4
421-
{PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1 // Connected to LCD_PSRAM_D5
422-
{PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2 // Connected to LCD_PSRAM_D6
423-
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3 // Connected to LCD_PSRAM_D7
424415
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 // Connected to ARD_D0
425416
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 // Connected to ARD_D1
426417
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 [N25Q128A13EF840F_DQ0]
427418
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 [N25Q128A13EF840F_DQ1]
428419
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
429-
// {PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2 // Connected to STDIO_UART_RX
430-
// {PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3 // Connected to STDIO_UART_TX
431420
{NC, NC, 0}
432421
};
433422

@@ -440,7 +429,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
440429

441430
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
442431
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to ARD_D4
443-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS // Connected to SD_D3
444432
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS [N25Q128A13EF840F_S]
445433
{NC, NC, 0}
446434
};

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PeripheralPins.c

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -404,30 +404,19 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
404404

405405
MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
406406
{PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
407-
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
408-
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
409407
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
410-
{PC_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
411-
{PC_5, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
412408
{PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
413409
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
414410
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
415-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
416411
{PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
417412
{PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
418413
{PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
419414
{PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
420-
{PE_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO0
421-
{PE_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO1
422-
{PE_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO2
423-
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK2_IO3
424415
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3
425416
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2
426417
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0
427418
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1
428419
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
429-
{PG_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO2
430-
{PG_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_IO3
431420
{NC, NC, 0}
432421
};
433422

@@ -440,7 +429,6 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
440429

441430
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
442431
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
443-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
444432
{PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]
445433
{NC, NC, 0}
446434
};

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/PinNames.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -306,14 +306,6 @@ typedef enum {
306306
SYS_WKUP2 = PC_0,
307307
SYS_WKUP3 = PC_1,
308308

309-
/**** QSPI pins ****/
310-
QSPI1_IO0 = PD_11,
311-
QSPI1_IO1 = PD_12,
312-
QSPI1_IO2 = PE_2,
313-
QSPI1_IO3 = PD_13,
314-
QSPI1_SCK = PB_2,
315-
QSPI1_CSN = PB_6,
316-
317309
// Not connected
318310
NC = (int)0xFFFFFFFF
319311
} PinName;

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/PeripheralPins.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -317,7 +317,6 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
317317
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
318318
{PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0
319319
{PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1
320-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
321320
{NC, NC, 0}
322321
};
323322

@@ -328,6 +327,5 @@ MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
328327

329328
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
330329
{PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS
331-
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK2_NCS
332330
{NC, NC, 0}
333331
};

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