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TomoYamanakaTomoYamanaka
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Modify IRQ handler processing without RTOS at Cortex-A IAR Compiler
In case of unusing RTOS, there is no processing against IRQ handler and it causes a linker error. Therefore, I added this processing with WEAK attribute. Also I added cmain.S file at cmsis/TARGET_CORTEX_A folder.
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  • cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR
  • targets/TARGET_RENESAS/TARGET_RZ_A1XX

3 files changed

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‎cmsis/TARGET_CORTEX_A/TOOLCHAIN_IAR/cmain.S

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/**************************************************
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*
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* Part two of the system initialization code, contains C-level
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* initialization, thumb-2 only variant.
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*
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* $Revision: 59783 $
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*
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**************************************************/
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/* Copyright 2008-2017, IAR Systems AB.
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This source code is the property of IAR Systems. The source code may only
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be used together with the IAR Embedded Workbench. Redistribution and use
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in source and binary forms, with or without modification, is permitted
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provided that the following conditions are met:
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- Redistributions of source code, in whole or in part, must retain the
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above copyright notice, this list of conditions and the disclaimer below.
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- IAR Systems name may not be used to endorse or promote products
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derived from this software without specific prior written permission.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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; --------------------------------------------------
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; Module ?cmain, C-level initialization.
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;
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SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
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SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
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SECTION .text:CODE:NOROOT(2)
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PUBLIC __cmain
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;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
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PUBLIC ?main
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EXTWEAK __iar_data_init3
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EXTWEAK __iar_argc_argv
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EXTERN __low_level_init
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EXTERN __call_ctors
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EXTERN main
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EXTERN exit
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EXTERN __iar_dynamic_initialization
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EXTERN mbed_sdk_init
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EXTERN mbed_main
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EXTERN SystemInit
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THUMB
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__cmain:
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?main:
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; Initialize segments.
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; __segment_init and __low_level_init are assumed to use the same
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; instruction set and to be reachable by BL from the ICODE segment
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; (it is safest to link them in segment ICODE).
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FUNCALL __cmain, __low_level_init
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bl __low_level_init
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cmp r0,#0
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beq ?l1
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FUNCALL __cmain, __iar_data_init3
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bl __iar_data_init3
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, mbed_sdk_init
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BL mbed_sdk_init
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, __iar_dynamic_initialization
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BL __iar_dynamic_initialization ; C++ dynamic initialization
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?l1:
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REQUIRE ?l3
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SECTION .text:CODE:NOROOT(2)
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PUBLIC _main
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PUBLIC _call_main
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THUMB
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__iar_init$$done: ; Copy initialization is done
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?l3:
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_call_main:
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, __iar_argc_argv
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BL __iar_argc_argv ; Maybe setup command line
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MOVS r0,#0 ; No parameters
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FUNCALL __cmain, mbed_main
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BL mbed_main
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FUNCALL __cmain, main
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BL main
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_main:
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FUNCALL __cmain, exit
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BL exit
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END

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_IAR/weak_handler.S

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/*
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* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Cortex-A Exception handlers
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*
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* -----------------------------------------------------------------------------
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*/
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NAME irq_weak.S
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MODE_SVC EQU 0x13
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PRESERVE8
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SECTION .text:CODE:NOROOT(2)
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PUBWEAK Undef_Handler
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Undef_Handler
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B .
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PUBWEAK SVC_Handler
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SVC_Handler
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B .
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PUBWEAK PAbt_Handler
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PAbt_Handler
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B .
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PUBWEAK DAbt_Handler
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DAbt_Handler
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B .
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PUBWEAK IRQ_Handler
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IRQ_Handler
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IMPORT IRQ_GetActiveIRQ
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IMPORT IRQ_GetHandler
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IMPORT IRQ_EndOfInterrupt
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SUB LR, LR, #4 ; Pre-adjust LR
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SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
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CPS #MODE_SVC ; Change to SVC mode
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PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
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MOV R3, SP ; Move SP into R3
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AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R3 ; Adjust stack
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PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
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BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
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MOV R4, R0 ; Move interrupt ID to R4
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BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
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CMP R0, #0 ; Check if handler address is 0
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BEQ IRQ_End ; If 0, end interrupt and return
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CPSIE i ; Re-enable interrupts
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BLX R0 ; Call IRQ handler
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CPSID i ; Disable interrupts
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IRQ_End
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MOV R0, R4 ; Move interrupt ID to R0
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BLX IRQ_EndOfInterrupt ; Signal end of interrupt
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POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
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ADD SP, SP, R3 ; Unadjust stack
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POP {R0-R3, R12, LR} ; Restore stacked APCS registers
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RFEFD SP! ; Return from IRQ handler
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END

‎targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/weak_handler.S

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/*
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* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* -----------------------------------------------------------------------------
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*
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* Project: CMSIS-RTOS RTX
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* Title: Cortex-A Exception handlers
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*
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* -----------------------------------------------------------------------------
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*/
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NAME irq_weak.S
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MODE_SVC EQU 0x13
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PRESERVE8
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SECTION .text:CODE:NOROOT(2)
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PUBWEAK Undef_Handler
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Undef_Handler
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B .
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PUBWEAK SVC_Handler
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SVC_Handler
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B .
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PUBWEAK PAbt_Handler
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PAbt_Handler
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B .
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PUBWEAK DAbt_Handler
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DAbt_Handler
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B .
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PUBWEAK IRQ_Handler
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IRQ_Handler
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IMPORT IRQ_GetActiveIRQ
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IMPORT IRQ_GetHandler
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IMPORT IRQ_EndOfInterrupt
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SUB LR, LR, #4 ; Pre-adjust LR
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SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
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CPS #MODE_SVC ; Change to SVC mode
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PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
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MOV R3, SP ; Move SP into R3
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AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
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SUB SP, SP, R3 ; Adjust stack
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PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
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BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
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MOV R4, R0 ; Move interrupt ID to R4
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BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
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CMP R0, #0 ; Check if handler address is 0
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BEQ IRQ_End ; If 0, end interrupt and return
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CPSIE i ; Re-enable interrupts
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BLX R0 ; Call IRQ handler
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CPSID i ; Disable interrupts
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IRQ_End
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MOV R0, R4 ; Move interrupt ID to R0
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BLX IRQ_EndOfInterrupt ; Signal end of interrupt
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POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
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ADD SP, SP, R3 ; Unadjust stack
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POP {R0-R3, R12, LR} ; Restore stacked APCS registers
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RFEFD SP! ; Return from IRQ handler
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END

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