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Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS
DISCO_H747I: add support of MBED_TICKLESS
2 parents 9f34b25 + 42a0407 commit 7177d8f

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33 files changed

+157
-116
lines changed

33 files changed

+157
-116
lines changed

‎features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
9393
return;
9494
}
9595
#if defined(DUAL_CORE)
96-
uint32_t timeout = HSEM_TIMEOUT;
97-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
96+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
9897
}
9998
#endif /* DUAL_CORE */
10099
/* Force the CRYP Periheral Clock Reset */

‎targets/TARGET_STM/TARGET_STM32F0/common_objects.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32f0xx_ll_usart.h"
3838
#include "stm32f0xx_ll_tim.h"
39+
#include "stm32f0xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {
@@ -119,6 +120,13 @@ struct analogin_s {
119120
uint8_t channel;
120121
};
121122

123+
124+
#ifdef CRC_PROG_POLYNOMIAL_SUPPORT
125+
#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32)
126+
#else
127+
#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 32 && (polynomial) == 0x04C11DB7)
128+
#endif
129+
122130
#include "gpio_object.h"
123131

124132
#if DEVICE_ANALOGOUT

‎targets/TARGET_STM/TARGET_STM32F1/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32f1xx_ll_usart.h"
3838
#include "stm32f1xx_ll_tim.h"
39+
#include "stm32f1xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32F2/objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32f2xx_ll_usart.h"
3838
#include "stm32f2xx_ll_tim.h"
39+
#include "stm32f2xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32F3/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32f3xx_ll_usart.h"
3838
#include "stm32f3xx_ll_tim.h"
39+
#include "stm32f3xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32F4/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32f4xx_ll_usart.h"
3838
#include "stm32f4xx_ll_tim.h"
39+
#include "stm32f4xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32F7/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
#include "stm32f7xx_ll_tim.h"
3939
#include "stm32f7xx_ll_adc.h"
4040
#include "stm32f7xx_ll_rtc.h"
41+
#include "stm32f7xx_ll_pwr.h"
4142

4243
#ifdef __cplusplus
4344
extern "C" {

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c

Lines changed: 0 additions & 23 deletions
This file was deleted.

‎targets/TARGET_STM/TARGET_STM32H7/analogin_device.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -89,8 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
8989
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
9090
PeriphClkInitStruct.PLL2.PLL2P = 4;
9191
#if defined(DUAL_CORE)
92-
uint32_t timeout = HSEM_TIMEOUT;
93-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
92+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
9493
}
9594
#endif /* DUAL_CORE */
9695
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -803,7 +803,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
803803
}
804804
else
805805
{
806-
return HAL_ERROR;
806+
/* Do not return HAL_ERROR if request repeats the current configuration */
807+
uint32_t temp1_pllckcfg = RCC->PLLCKSELR;
808+
uint32_t temp2_pllckcfg = RCC->PLL1DIVR;
809+
if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
810+
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
811+
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
812+
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
813+
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
814+
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
815+
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
816+
{
817+
return HAL_ERROR;
818+
}
807819
}
808820
}
809821
return HAL_OK;

‎targets/TARGET_STM/TARGET_STM32H7/flash_api.c

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,7 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId);
2828
int32_t flash_init(flash_t *obj)
2929
{
3030
#if defined(DUAL_CORE)
31-
uint32_t timeout = HSEM_TIMEOUT;
32-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
31+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
3332
}
3433
#endif /* DUAL_CORE */
3534
/* Clear pending flags (if any) */
@@ -58,8 +57,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
5857
}
5958

6059
#if defined(DUAL_CORE)
61-
uint32_t timeout = HSEM_TIMEOUT;
62-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
60+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
6361
}
6462
#endif /* DUAL_CORE */
6563
if (HAL_FLASH_Unlock() != HAL_OK) {
@@ -121,8 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
121119
}
122120

123121
#if defined(DUAL_CORE)
124-
uint32_t timeout = HSEM_TIMEOUT;
125-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
122+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
126123
}
127124
#endif /* DUAL_CORE */
128125
if (HAL_FLASH_Unlock() != HAL_OK) {

‎targets/TARGET_STM/TARGET_STM32H7/objects.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@
4040
#if defined(DUAL_CORE)
4141
#include "stm32h7xx_ll_hsem.h"
4242
#include "stm32h7xx_ll_rcc.h"
43-
#include "stm32h7xx_ll_pwr.h"
4443
#include "stm32h7xx_ll_cortex.h"
4544
#endif /* CONFIG_STM32H7_DUAL_CORE */
45+
#include "stm32h7xx_ll_pwr.h"
4646

4747
#ifdef __cplusplus
4848
extern "C" {
@@ -151,8 +151,8 @@ struct analogin_s {
151151
#if defined(DUAL_CORE)
152152
/* HW semaphore Complement ID list defined in hw_conf.h from STM32WB */
153153
/* Index of the semaphore used to manage the entry Stop Mode procedure */
154-
#define CFG_HW_ENTRY_STOP_MODE_SEMID 4
155-
#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1 << CFG_HW_ENTRY_STOP_MODE_SEMID)
154+
#define CFG_HW_STOP_MODE_SEMID 4
155+
#define CFG_HW_STOP_MODE_MASK_SEMID (1 << CFG_HW_STOP_MODE_SEMID)
156156

157157
/* Index of the semaphore used to access the RCC */
158158
#define CFG_HW_RCC_SEMID 3

‎targets/TARGET_STM/TARGET_STM32H7/pin_device.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,7 @@ static inline void stm_pin_DisconnectDebug(PinName pin)
4545
static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
4646
{
4747
#if defined(DUAL_CORE)
48-
uint32_t timeout = HSEM_TIMEOUT;
49-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
48+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
5049
}
5150
#endif /* DUAL_CORE */
5251

@@ -72,8 +71,7 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
7271
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
7372

7473
#if defined(DUAL_CORE)
75-
uint32_t timeout = HSEM_TIMEOUT;
76-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
74+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
7775
}
7876
#endif /* DUAL_CORE */
7977

‎targets/TARGET_STM/TARGET_STM32L0/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32l0xx_ll_usart.h"
3838
#include "stm32l0xx_ll_tim.h"
39+
#include "stm32l0xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32L1/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "PinNames.h"
3737
#include "stm32l1xx_ll_usart.h"
3838
#include "stm32l1xx_ll_tim.h"
39+
#include "stm32l1xx_ll_pwr.h"
3940

4041
#ifdef __cplusplus
4142
extern "C" {

‎targets/TARGET_STM/TARGET_STM32L4/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
#include "stm32l4xx_ll_lpuart.h"
3939
#include "stm32l4xx_ll_tim.h"
4040
#include "stm32l4xx_ll_rtc.h"
41+
#include "stm32l4xx_ll_pwr.h"
4142

4243
#ifdef __cplusplus
4344
extern "C" {

‎targets/TARGET_STM/TARGET_STM32WB/common_objects.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
#include "PinNames.h"
3939
#include "stm32wbxx_ll_usart.h"
4040
#include "stm32wbxx_ll_tim.h"
41+
#include "stm32wbxx_ll_pwr.h"
4142

4243
#ifdef __cplusplus
4344
extern "C" {

‎targets/TARGET_STM/can_api.c

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,7 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
8787
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
8888
RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
8989
#if defined(DUAL_CORE)
90-
uint32_t timeout = HSEM_TIMEOUT;
91-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
90+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
9291
}
9392
#endif /* DUAL_CORE */
9493
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@@ -229,8 +228,7 @@ void can_irq_free(can_t *obj)
229228
void can_free(can_t *obj)
230229
{
231230
#if defined(DUAL_CORE)
232-
uint32_t timeout = HSEM_TIMEOUT;
233-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
231+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
234232
}
235233
#endif /* DUAL_CORE */
236234
__HAL_RCC_FDCAN_FORCE_RESET();
@@ -716,8 +714,7 @@ void can_free(can_t *obj)
716714
{
717715
CANName can = (CANName) obj->CanHandle.Instance;
718716
#if defined(DUAL_CORE)
719-
uint32_t timeout = HSEM_TIMEOUT;
720-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
717+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
721718
}
722719
#endif /* DUAL_CORE */
723720
// Reset CAN and disable clock

‎targets/TARGET_STM/gpio_api.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,8 +156,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
156156
inline void gpio_dir(gpio_t *obj, PinDirection direction)
157157
{
158158
#if defined(DUAL_CORE)
159-
uint32_t timeout = HSEM_TIMEOUT;
160-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
159+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
161160
}
162161
#endif /* DUAL_CORE */
163162

‎targets/TARGET_STM/gpio_object.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,7 @@ typedef struct {
5858
static inline void gpio_write(gpio_t *obj, int value)
5959
{
6060
#if defined(DUAL_CORE)
61-
uint32_t timeout = HSEM_TIMEOUT;
62-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
61+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
6362
}
6463
#endif /* DUAL_CORE */
6564

‎targets/TARGET_STM/i2c_api.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -215,8 +215,7 @@ void i2c_hw_reset(i2c_t *obj)
215215
timeout = BYTE_TIMEOUT;
216216
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
217217
#if defined(DUAL_CORE)
218-
timeout = HSEM_TIMEOUT;
219-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
218+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
220219
}
221220
#endif /* DUAL_CORE */
222221
#if defined I2C1_BASE
@@ -452,8 +451,7 @@ void i2c_frequency(i2c_t *obj, int hz)
452451

453452
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
454453
#if defined(DUAL_CORE)
455-
timeout = HSEM_TIMEOUT;
456-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
454+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
457455
}
458456
#endif /* DUAL_CORE */
459457
#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)

‎targets/TARGET_STM/lp_ticker.c

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,13 @@
6767
#define LPTIM_MST_IRQ LPTIM4_IRQn
6868
#define LPTIM_MST_RCC __HAL_RCC_LPTIM4_CLK_ENABLE
6969

70+
#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM4_CLKAM_ENABLE
71+
72+
/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
73+
#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\
74+
HAL_EXTI_D1_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, ENABLE);\
75+
HAL_EXTI_D2_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, DISABLE);\
76+
}
7077
#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM4_FORCE_RESET
7178
#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM4_RELEASE_RESET
7279

@@ -85,6 +92,13 @@
8592
#define LPTIM_MST_IRQ LPTIM5_IRQn
8693
#define LPTIM_MST_RCC __HAL_RCC_LPTIM5_CLK_ENABLE
8794

95+
#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM5_CLKAM_ENABLE
96+
97+
/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
98+
#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\
99+
HAL_EXTI_D2_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, ENABLE);\
100+
HAL_EXTI_D1_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, DISABLE);\
101+
}
88102
#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM5_FORCE_RESET
89103
#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM5_RELEASE_RESET
90104
#else
@@ -191,8 +205,7 @@ void lp_ticker_init(void)
191205

192206
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
193207
#if defined(DUAL_CORE)
194-
uint32_t timeout = HSEM_TIMEOUT;
195-
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
208+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
196209
}
197210
#endif /* DUAL_CORE */
198211
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -209,6 +222,10 @@ void lp_ticker_init(void)
209222
LPTIM_MST_RESET_ON();
210223
LPTIM_MST_RESET_OFF();
211224
#if defined(DUAL_CORE)
225+
/* Configure EXTI wakeup and configure autonomous mode */
226+
LPTIM_MST_RCC_CLKAM();
227+
LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
228+
212229
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
213230
#endif /* DUAL_CORE */
214231

‎targets/TARGET_STM/mbed_overrides.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ void mbed_sdk_init()
6060
/* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization. */
6161

6262
/* Activate HSEM notification for Cortex-M4*/
63-
LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
63+
LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
6464

6565
/*
6666
* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
@@ -89,7 +89,8 @@ void mbed_sdk_init()
8989
LL_LPM_EnableSleep();
9090

9191
/* Clear HSEM flag */
92-
LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
92+
LL_HSEM_DisableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
93+
LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
9394
}
9495

9596
// Update the SystemCoreClock variable.
@@ -109,9 +110,9 @@ void mbed_sdk_init()
109110
/* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization.
110111
otherwise CM7 should wakeup CM4 when system clocks initialization is done. */
111112
if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
112-
LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
113+
LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID);
113114
/*Release HSEM in order to notify the CPU2(CM4)*/
114-
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
115+
LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, 0);
115116
} else {
116117
LL_RCC_ForceCM4Boot();
117118
}

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