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Merge pull request #10631 from VVESTM/update_cube_h7
Update cube h7 to 1.4.0
2 parents 3f756f0 + d8e1e43 commit 80d7cb2

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‎targets/TARGET_STM/README.md

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ This table summarizes the STM32Cube versions currently used :
1818
| F3 | 1.9.0 |
1919
| F4 | 1.19.0 |
2020
| F7 | 1.10.0 |
21+
| H7 | 1.4.0 |
2122
| L0 | 1.10.0 |
2223
| L1 | 1.8.1 |
2324
| L4 | 1.11.0 |

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32h743xx.S

Lines changed: 2 additions & 2 deletions
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@@ -14,8 +14,8 @@
1414
;******************************************************************************
1515
;* @attention
1616
;*
17-
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
;* All rights reserved.</center></h2>
17+
;* Copyright (c) 2017 STMicroelectronics.
18+
;* All rights reserved.
1919
;*
2020
;* This software component is licensed by ST under BSD 3-Clause license,
2121
;* the "License"; You may not use this file except in compliance with the

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@
1414
;******************************************************************************
1515
;* @attention
1616
;*
17-
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
;* All rights reserved.</center></h2>
17+
;* Copyright (c) 2017 STMicroelectronics.
18+
;* All rights reserved.
1919
;*
2020
;* This software component is licensed by ST under BSD 3-Clause license,
2121
;* the "License"; You may not use this file except in compliance with the

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/startup_stm32h743xx.S

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -292,7 +292,6 @@ g_pfnVectors:
292292
.word LPUART1_IRQHandler /* LP UART1 interrupt */
293293
.word 0 /* Reserved */
294294
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
295-
.word 0 /* Reserved */
296295
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
297296
.word SAI4_IRQHandler /* SAI4 global interrupt */
298297
.word 0 /* Reserved */

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h

Lines changed: 205 additions & 171 deletions
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‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h7xx.h

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,17 +58,26 @@
5858
application
5959
*/
6060

61-
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx)
62-
// MBED PATCH
63-
#define STM32H743xx /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
61+
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
62+
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
63+
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
64+
// MBED PATCH
65+
#define STM32H743xx /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
6466
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
6567
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
68+
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
69+
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
70+
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
71+
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
6672
#endif
6773

6874
/* Tip: To avoid modifying this file each time you need to switch between these
6975
devices, you can define the device in your toolchain compiler preprocessor.
7076
*/
7177

78+
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
79+
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
80+
#endif
7281

7382
#if !defined (USE_HAL_DRIVER)
7483
/**
@@ -82,10 +91,10 @@
8291
#define USE_FULL_LL_DRIVER // MBED PATCH
8392

8493
/**
85-
* @brief CMSIS Device version number V1.4.0
94+
* @brief CMSIS Device version number V1.5.0
8695
*/
8796
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
88-
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
97+
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
8998
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
9099
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
91100
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -107,6 +116,16 @@
107116
#include "stm32h753xx.h"
108117
#elif defined(STM32H750xx)
109118
#include "stm32h750xx.h"
119+
#elif defined(STM32H742xx)
120+
#include "stm32h742xx.h"
121+
#elif defined(STM32H745xx)
122+
#include "stm32h745xx.h"
123+
#elif defined(STM32H755xx)
124+
#include "stm32h755xx.h"
125+
#elif defined(STM32H747xx)
126+
#include "stm32h747xx.h"
127+
#elif defined(STM32H757xx)
128+
#include "stm32h757xx.h"
110129
#else
111130
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
112131
#endif

‎targets/TARGET_STM/TARGET_STM32H7/device/stm32_hal_legacy.h

Lines changed: 96 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -236,6 +236,11 @@
236236
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
237237
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
238238

239+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
240+
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
241+
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
242+
#endif
243+
239244
/**
240245
* @}
241246
*/
@@ -486,6 +491,7 @@
486491
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
487492
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
488493
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
494+
489495
/**
490496
* @}
491497
*/
@@ -599,6 +605,7 @@
599605
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
600606
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
601607
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
608+
602609
/**
603610
* @}
604611
*/
@@ -738,6 +745,12 @@
738745
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
739746
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
740747

748+
#if defined(STM32L1) || defined(STM32L4)
749+
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
750+
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
751+
#endif
752+
753+
741754
/**
742755
* @}
743756
*/
@@ -753,7 +766,6 @@
753766

754767
#define I2S_FLAG_TXE I2S_FLAG_TXP
755768
#define I2S_FLAG_RXNE I2S_FLAG_RXP
756-
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
757769
#endif
758770

759771
#if defined(STM32F7)
@@ -971,6 +983,24 @@
971983
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
972984
#endif
973985

986+
#if defined(STM32H7)
987+
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
988+
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
989+
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
990+
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
991+
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
992+
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
993+
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
994+
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
995+
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
996+
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
997+
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
998+
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
999+
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
1000+
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
1001+
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
1002+
#endif
1003+
9741004
/**
9751005
* @}
9761006
*/
@@ -1250,7 +1280,7 @@
12501280

12511281
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
12521282

1253-
#if defined(STM32H7) || defined(STM32G0)
1283+
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
12541284
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
12551285
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
12561286
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@@ -1259,7 +1289,18 @@
12591289
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
12601290
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
12611291
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
1262-
#endif /* STM32H7 || STM32G0 */
1292+
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
1293+
1294+
#if defined(STM32F4)
1295+
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
1296+
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
1297+
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
1298+
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
1299+
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
1300+
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
1301+
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
1302+
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
1303+
#endif /* STM32F4 */
12631304
/**
12641305
* @}
12651306
*/
@@ -1339,7 +1380,7 @@
13391380
#define HAL_TIM_DMAError TIM_DMAError
13401381
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
13411382
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
1342-
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
1383+
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
13431384
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
13441385
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
13451386
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -2235,6 +2276,20 @@
22352276
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
22362277
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
22372278

2279+
#if defined(STM32WB)
2280+
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
2281+
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
2282+
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
2283+
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
2284+
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
2285+
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
2286+
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
2287+
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
2288+
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
2289+
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
2290+
#define QSPI_IRQHandler QUADSPI_IRQHandler
2291+
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
2292+
22382293
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
22392294
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
22402295
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2451,12 +2506,28 @@
24512506
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
24522507
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
24532508
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
2509+
2510+
#if defined(STM32H7)
2511+
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
2512+
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
2513+
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
2514+
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
2515+
2516+
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
2517+
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
2518+
2519+
2520+
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
2521+
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
2522+
#endif
2523+
24542524
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
24552525
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
24562526
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
24572527
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
24582528
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
24592529
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
2530+
24602531
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
24612532
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
24622533
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@@ -2789,6 +2860,15 @@
27892860
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
27902861
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
27912862

2863+
#if defined(STM32L1)
2864+
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
2865+
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
2866+
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
2867+
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
2868+
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
2869+
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
2870+
#endif /* STM32L1 */
2871+
27922872
#if defined(STM32F4)
27932873
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
27942874
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@@ -2905,7 +2985,7 @@
29052985

29062986
#if defined(STM32L4)
29072987
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
2908-
#elif defined(STM32G0)
2988+
#elif defined(STM32WB) || defined(STM32G0)
29092989
#else
29102990
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
29112991
#endif
@@ -3149,7 +3229,7 @@
31493229
#define SDIO_IRQHandler SDMMC1_IRQHandler
31503230
#endif
31513231

3152-
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
3232+
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
31533233
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
31543234
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
31553235
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@@ -3408,6 +3488,16 @@
34083488
* @}
34093489
*/
34103490

3491+
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
3492+
* @{
3493+
*/
3494+
#if defined (STM32L4)
3495+
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
3496+
#endif
3497+
/**
3498+
* @}
3499+
*/
3500+
34113501
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
34123502
* @{
34133503
*/

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